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path: root/stm32-metapac/build.rs
AgeCommit message (Expand)Author
2022-06-12Run rustfmt.Dario Nieuwenhuis
2022-03-28Convert chip name to upper case to fix rebuildsNikita Strygin
2022-03-15Merge #667bors[bot]
2022-03-15Remove duplicate stm32-metapac/src/common.rs with chiptoolNicolas Viennot
2022-03-15Rebuild when the chip definition changesNicolas Viennot
2022-02-26stm32-metapac: remove all macrotables, deduplicate metadata files.Dario Nieuwenhuis
2021-11-23stm32: rename core features from _cmX to -cmX, cleanup gen.Dario Nieuwenhuis
2021-09-21Support for STM32L1Ulf Lilleengen
2021-08-02Use an em bikeshed instead of an underscore bikeshed.Bob McWhirter
2021-08-02Put the implicit memory.x behind a `memory_x` feature on embassy-stm32.Bob McWhirter
2021-06-10stm32-metapac: add new codegen, allows pregenerating the entire pacDario Nieuwenhuis
2021-06-09Make RCC lookup optionalUlf Lilleengen
2021-06-09Cleanup and fix l4sUlf Lilleengen
2021-06-09Generate clock peripherals for all peripherals with register blockUlf Lilleengen
2021-06-08Handle other L4 variantsUlf Lilleengen
2021-06-08Workaround for L4Ulf Lilleengen
2021-06-08Add workaround for STM32H7Ulf Lilleengen
2021-06-08Auto generate SPI v2 clock enableUlf Lilleengen
2021-06-07stm32-metapac: Do not generate cfgs metadataDario Nieuwenhuis
2021-06-03Remove the exti_interrupts table.Bob McWhirter
2021-06-03Migrate exti_irq stuff to macro tables.Bob McWhirter
2021-06-03Move DAC, I2C, SPI and RNG to macro-tables.Bob McWhirter
2021-06-03Remove the Option around the pins Vec.Bob McWhirter
2021-06-03Create the new peripheral_pins! macro table.Bob McWhirter
2021-06-01Fix L4+ family cfgDario Nieuwenhuis
2021-05-31Add stm32-metapac crate, with codegen in rustDario Nieuwenhuis
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 17:09:22 +0000