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path: root/doc/ale-verilog.txt
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2021-07-12Add Yosys linter for Verilog files. (#3713)Nathan Sharp
* Add yosys for verilog files. * Add handler test for yosys. * fix typo in yosys handler test * fix array order in yosys handler test * add yosys linter to filetype defaults test * fix duplicate tag * add 'yosys' to 'ale-supported-languages-and-tools.txt'
2020-08-06Adds hdl_checker LSP support (#2804)Andre Souto
* Added hdl_checker support * Added hdl_checker tests HDL Checker searches for files when no config file is found, which could lead to very long searches when the user is not really on a project setting
2019-01-27Add VHDL Support & Newer Verilog Linters (#2229)John Gentile
* Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
2017-07-08Use equal signs for language documentation sectionsw0rp
2017-06-29Adds an option to pass additional arguments to the verilog/verilator … (#698)Tarik Graba
* Adds an option to pass additional arguments to the verilog/verilator linter The new otion is g:ale_verilog_verilator_options + doc * Spell check verilog linter doc file * Add entries to the verilog linters in the doc table of content * Vader test for verilog/verilator linter args option verilog_verilator_options