Add VHDL Support & Newer Verilog Linters (#2229)

* Added VHDL file support with ghdl compiler
* Update ghdl.vim
* Create vcom.vim
* Create xvhdl.vim
* Update xvlog.vim
* Added documentation for VHDL & Verilog linters
* Added tests to VHDL & Verilog linters

1 files changed, 36 insertions, 0 deletions

diff --git a/ale_linters/verilog/vlog.vim b/ale_linters/verilog/vlog.vim
new file mode 100644
index 00000000..1a1fcb6a
--- /dev/null
+++ b/ale_linters/verilog/vlog.vim
@@ -0,0 +1,36 @@
+" Author:      John Gentile <johncgentile17@gmail.com>
+" Description: Adds support for Mentor Graphics Questa/ModelSim `vlog` Verilog compiler/checker
+
+call ale#Set('verilog_vlog_executable', 'vlog')
+" See `$ vlog -h` for more options
+call ale#Set('verilog_vlog_options', '-quiet -lint')
+
+function! ale_linters#verilog#vlog#GetCommand(buffer) abort
+    return '%e ' . ale#Pad(ale#Var(a:buffer, 'verilog_vlog_options')) . ' %t'
+endfunction
+
+function! ale_linters#verilog#vlog#Handle(buffer, lines) abort
+    "Matches patterns like the following:
+    "** Warning: add.v(7): (vlog-2623) Undefined variable: C.
+    "** Error: file.v(1): (vlog-13294) Identifier must be declared with a port mode: C.
+    let l:pattern = '^**\s\(\w*\):[a-zA-Z0-9\-\.\_\/ ]\+(\(\d\+\)):\s\+\(.*\)'
+    let l:output = []
+
+    for l:match in ale#util#GetMatches(a:lines, l:pattern)
+      call add(l:output, {
+      \   'lnum': l:match[2] + 0,
+      \   'type': l:match[1] is? 'Error' ? 'E' : 'W',
+      \   'text': l:match[3],
+      \})
+    endfor
+
+    return l:output
+endfunction
+
+call ale#linter#Define('verilog', {
+\   'name': 'vlog',
+\   'output_stream': 'stdout',
+\   'executable_callback': ale#VarFunc('verilog_vlog_executable'),
+\   'command_callback': 'ale_linters#verilog#vlog#GetCommand',
+\   'callback': 'ale_linters#verilog#vlog#Handle',
+\})