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| author | Michael Clark <mjc@sifive.com> | 2018-03-05 20:22:30 +1300 |
|---|---|---|
| committer | Michael Clark <mjc@sifive.com> | 2018-05-06 10:39:38 +1200 |
| commit | 89854803ce3efb16fbc94604e652f152f5102569 (patch) | |
| tree | 8c517efe0a2718ff6ce514d167e2205b8d8a7cfa /target/riscv | |
| parent | 5b5583806b16ca9ddc454e2a5892b1fea575e470 (diff) | |
| download | qemu-89854803ce3efb16fbc94604e652f152f5102569.zip | |
RISC-V: Remove EM_RISCV ELF_MACHINE indirection
Pointless indirection. Other ports use EM_ constants directly.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 41e06ac0f9..9871e6feb1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -34,7 +34,6 @@ #define TCG_GUEST_DEFAULT_MO 0 -#define ELF_MACHINE EM_RISCV #define CPUArchState struct CPURISCVState #include "qemu-common.h" |