From 89854803ce3efb16fbc94604e652f152f5102569 Mon Sep 17 00:00:00 2001
From: Michael Clark <mjc@sifive.com>
Date: Mon, 5 Mar 2018 20:22:30 +1300
Subject: RISC-V: Remove EM_RISCV ELF_MACHINE indirection
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Pointless indirection. Other ports use EM_ constants directly.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'target/riscv')

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 41e06ac0f9..9871e6feb1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -34,7 +34,6 @@
 
 #define TCG_GUEST_DEFAULT_MO 0
 
-#define ELF_MACHINE EM_RISCV
 #define CPUArchState struct CPURISCVState
 
 #include "qemu-common.h"
-- 
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