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| author | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2013-10-24 19:03:44 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2013-10-24 22:32:56 +0200 |
| commit | bb3cb951ef530da7d248051347c974e4d20e6ea0 (patch) | |
| tree | 30129d20f52f96272555720589ff3a27cc077212 /target-microblaze/translate.c | |
| parent | a235900e225d21237a13333eaff40198974bc861 (diff) | |
| download | qemu-bb3cb951ef530da7d248051347c974e4d20e6ea0.zip | |
microblaze: Improve srl
write_carry only looks at bit zero, no need to mask out the others.
Meassured a 12% speed improvement in linux-user srl loops.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'target-microblaze/translate.c')
| -rw-r--r-- | target-microblaze/translate.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 916db15c99..93aafac691 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -780,13 +780,10 @@ static void dec_bit(DisasContext *dc) case 0x1: case 0x41: /* srl. */ - t0 = tcg_temp_new(); LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); - /* Update carry. */ - tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1); - write_carry(dc, t0); - tcg_temp_free(t0); + /* Update carry. Note that write carry only looks at the LSB. */ + write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { if (op == 0x41) tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1); |