From bb3cb951ef530da7d248051347c974e4d20e6ea0 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Thu, 24 Oct 2013 19:03:44 +0200 Subject: microblaze: Improve srl write_carry only looks at bit zero, no need to mask out the others. Meassured a 12% speed improvement in linux-user srl loops. Signed-off-by: Edgar E. Iglesias --- target-microblaze/translate.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'target-microblaze/translate.c') diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 916db15c99..93aafac691 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -780,13 +780,10 @@ static void dec_bit(DisasContext *dc) case 0x1: case 0x41: /* srl. */ - t0 = tcg_temp_new(); LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); - /* Update carry. */ - tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1); - write_carry(dc, t0); - tcg_temp_free(t0); + /* Update carry. Note that write carry only looks at the LSB. */ + write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { if (op == 0x41) tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1); -- cgit v1.2.3