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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-14 01:32:12 +0100 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2020-12-17 10:34:59 +0100 |
| commit | 388765a05bde86de9d9b66348afed6551c58f091 (patch) | |
| tree | 899871a522f0ccdb60a047667c348491e06df027 /linux-user/elfload.c | |
| parent | 7d9a3d96f57dfed441622ebb9d1516473d51f919 (diff) | |
| download | qemu-388765a05bde86de9d9b66348afed6551c58f091.zip | |
linux-user/elfload: Introduce MIPS GET_FEATURE_REG_SET() macro
ISA features are usually denoted in read-only bits from
CPU registers. Add the GET_FEATURE_REG_SET() macro which
checks if a CPU register has bits set.
Use the macro to check for MSA (which sets the MSAP bit of
the Config3 register when the ASE implementation is present).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214003215.344522-4-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'linux-user/elfload.c')
| -rw-r--r-- | linux-user/elfload.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 0e1d7e7677..b7c6d30723 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -992,17 +992,21 @@ enum { #define GET_FEATURE_INSN(_flag, _hwcap) \ do { if (cpu->env.insn_flags & (_flag)) { hwcaps |= _hwcap; } } while (0) +#define GET_FEATURE_REG_SET(_reg, _mask, _hwcap) \ + do { if (cpu->env._reg & (_mask)) { hwcaps |= _hwcap; } } while (0) + static uint32_t get_elf_hwcap(void) { MIPSCPU *cpu = MIPS_CPU(thread_cpu); uint32_t hwcaps = 0; GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6); - GET_FEATURE_INSN(ASE_MSA, HWCAP_MIPS_MSA); + GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA); return hwcaps; } +#undef GET_FEATURE_REG_SET #undef GET_FEATURE_INSN #endif /* TARGET_MIPS */ |