From 388765a05bde86de9d9b66348afed6551c58f091 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 14 Dec 2020 01:32:12 +0100 Subject: linux-user/elfload: Introduce MIPS GET_FEATURE_REG_SET() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ISA features are usually denoted in read-only bits from CPU registers. Add the GET_FEATURE_REG_SET() macro which checks if a CPU register has bits set. Use the macro to check for MSA (which sets the MSAP bit of the Config3 register when the ASE implementation is present). Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201214003215.344522-4-f4bug@amsat.org> Signed-off-by: Laurent Vivier --- linux-user/elfload.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'linux-user/elfload.c') diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 0e1d7e7677..b7c6d30723 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -992,17 +992,21 @@ enum { #define GET_FEATURE_INSN(_flag, _hwcap) \ do { if (cpu->env.insn_flags & (_flag)) { hwcaps |= _hwcap; } } while (0) +#define GET_FEATURE_REG_SET(_reg, _mask, _hwcap) \ + do { if (cpu->env._reg & (_mask)) { hwcaps |= _hwcap; } } while (0) + static uint32_t get_elf_hwcap(void) { MIPSCPU *cpu = MIPS_CPU(thread_cpu); uint32_t hwcaps = 0; GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6); - GET_FEATURE_INSN(ASE_MSA, HWCAP_MIPS_MSA); + GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA); return hwcaps; } +#undef GET_FEATURE_REG_SET #undef GET_FEATURE_INSN #endif /* TARGET_MIPS */ -- cgit v1.2.3