blob: 05877b553abc3cb8b96ff7443ce690c82667589e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
|
# $FreeBSD$
PORTNAME= verilator
PORTVERSION= 4.008
PORTREVISION= 2
CATEGORIES= cad
MASTER_SITES= https://www.veripool.org/ftp/
MAINTAINER= kevinz5000@gmail.com
COMMENT= Synthesizable Verilog to C++ compiler
LICENSE= GPLv3
LICENSE_FILE= ${WRKSRC}/COPYING
USES= bison compiler:c++11-lang gmake pathfix perl5 tar:tgz
GNU_CONFIGURE= yes
CONFIGURE_ENV= INSTALL_PROGRAM="${INSTALL_SCRIPT}"
post-patch:
${REINPLACE_CMD} -e 's|@pkgconfigdir@|${PREFIX}/libdata/pkgconfig|' \
${WRKSRC}/Makefile.in
post-build:
@${STRIP_CMD} ${WRKSRC}/bin/verilator_bin
post-install:
${RM} ${STAGEDIR}${PREFIX}/bin/verilator_bin_dbg ${STAGEDIR}${PREFIX}/bin/verilator_coverage_bin_dbg
.include <bsd.port.mk>
|
