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AgeCommit message (Expand)Author
2023-03-21all: expire ports depending on cad/py-ocd on 2023-06-21Rene Ladan
2023-03-20cad/leocad: Update 21.06 → 23.03Yuri Victorovich
2023-03-19cad/NASTRAN-95: Remove expired port:Muhammad Moinur Rahman
2023-03-19cad/py-ezdxf: Update to 1.0.2Wen Heping
2023-03-16editors/lazarus: Bump PORTREVISION of dependant portsJose Alonso Cardenas Marquez
2023-03-16lang/rust: Bump revisions after 1.68.0Mikael Urankar
2023-03-14cad/qrouter: Update 1.4.85 → 1.4.86Yuri Victorovich
2023-03-14cad/kicad: backport powerpc build fix from kicad-develPiotr Kubaj
2023-03-13cad/zcad: try to unbreak the build of the port's Qt5 flavorAlexey Dokuchaev
2023-03-13cad/openvsp: fix build without libompPiotr Kubaj
2023-03-13cad/libopencad: fix build on armv? / powerpcPiotr Kubaj
2023-03-12cad/kicad: update KiCad and libraries to 7.0.1Christoph Moench-Tegeder
2023-03-12cad/nvc: Update 1.8.1 → 1.8.2Yuri Victorovich
2023-03-11cad/surelog: Add PORTSCOUT lineYuri Victorovich
2023-03-11cad/netgen-lvs: Update 1.5.249 → 1.5.250Yuri Victorovich
2023-03-09graphics/proj: Update to 9.2.0Loïc Bartoletti
2023-03-09PyQt: Update to latest versionsLoïc Bartoletti
2023-03-09cad/netgen-lvs: Update 1.5.237 → 1.5.249Yuri Victorovich
2023-03-08cad/surelog: Update 1.45 → 1.48Yuri Victorovich
2023-03-08cad/ghdl: Update 2.0.0-20230222 → 3.0.0Yuri Victorovich
2023-03-08cad/netgen: Update to 6.2.2302.Stephen Montgomery-Smith
2023-03-06cad/yosys: Update 0.26 → 0.27Yuri Victorovich
2023-03-06cad/svls: Update 0.2.6 → 0.2.7Yuri Victorovich
2023-03-05cad/verilator: Update 5.006 → 5.008Yuri Victorovich
2023-03-06cad/sweethome3d: update Sweet Home 3D to version 7.1Alexey Dokuchaev
2023-03-05cad/veryl: Update 0.5.2 → 0.5.5Yuri Victorovich
2023-03-05cad/veroroute: Update 2.28 → 2.29Yuri Victorovich
2023-03-05cad/openvsp: update to 3.32.1Fernando Apesteguía
2023-03-04*: Bump PORTREVISION of math/Imath usersMatthias Andree
2023-03-03devel/onetbb: Update to 2021.8.0Ganael LAPLANCHE
2023-03-02cad/gdscpp: New port: C++ library to create and read GDSII fileYuri Victorovich
2023-03-01cad/veryl: Update 0.5.0 → 0.5.2Yuri Victorovich
2023-03-02accessibility/at-spi2-core: update to 2.46.0Tobias C. Berner
2023-02-25cad/zcad: mark qt5 flavor BROKENAntoine Brodin
2023-02-24cad/geda: unbreak the port's build (specifically, linking)Alexey Dokuchaev
2023-02-23cad/ghdl: Correct DISTVERSIONYuri Victorovich
2023-02-23cad/ghdl: Re-add port: GNU VHDL simulatorYuri Victorovich
2023-02-23cad/geda: make the port's code consumable by contemporary compilersAlexey Dokuchaev
2023-02-22cad/py-vunit-hdl: Update 4.6.0 → 4.6.2Yuri Victorovich
2023-02-22cad/veryl: Update 0.3.4 → 0.5.0Yuri Victorovich
2023-02-21cad/verilator: Improve how python executable path is passed to the buildYuri Victorovich
2023-02-21cad/kicad: fix clang options on 32bit platformsChristoph Moench-Tegeder
2023-02-21cad/verilator: Fix wrong PYTHON3 path in installed makefileYuri Victorovich
2023-02-20cad/py-ocp: deprecateAntoine Brodin
2023-02-20cad/NASTRAN-95: deprecateAntoine Brodin
2023-02-20cad/geda: deprecateAntoine Brodin
2023-02-20cad/gtkwave: Adopt/Update to 3.3.114Nuno Teixeira
2023-02-18cad/hs-verismith: Add PORTSCOUT tagYuri Victorovich
2023-02-17cad/hs-verismith: New port: Verilog fuzzerYuri Victorovich
2023-02-13lang/rust: Bump revisions after 1.67.1Mikael Urankar
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