Adds hdl_checker LSP support (#2804)

* Added hdl_checker support
* Added hdl_checker tests

HDL Checker searches for files when no config file is found, which could lead to very long searches when the user is not really on a project setting

3 files changed, 89 insertions, 6 deletions

diff --git a/doc/ale-verilog.txt b/doc/ale-verilog.txt
index 94b820b8..01af63c2 100644
--- a/doc/ale-verilog.txt
+++ b/doc/ale-verilog.txt
@@ -3,7 +3,10 @@ ALE Verilog/SystemVerilog Integration                     *ale-verilog-options*
 
 
 ===============================================================================
-ALE can use four different linters for Verilog HDL:
+ALE can use five different linters for Verilog HDL:
+
+  HDL Checker
+    Using `hdl_checker --lsp`
 
   iverilog:
     Using `iverilog -t null -Wall`
@@ -26,6 +29,9 @@ defining 'g:ale_linters' variable:
     \ let g:ale_linters = {'systemverilog' : ['verilator'],}
 <
 
+===============================================================================
+General notes
+
 Linters/compilers that utilize a "work" directory for analyzing designs- such
 as ModelSim and Vivado- can be passed the location of these directories as
 part of their respective option strings listed below. This is useful for
@@ -40,6 +46,16 @@ changing. This can happen in the form of hangs or crashes. To help prevent
 this when using these linters, it may help to run linting less frequently; for
 example, only when a file is saved.
 
+HDL Checker is an alternative for some of the issues described above. It wraps
+around ghdl, Vivado and ModelSim/Questa and, when using the latter, it can
+handle mixed language (VHDL, Verilog, SystemVerilog) designs.
+
+===============================================================================
+hdl-checker                                           *ale-verilog-hdl-checker*
+
+See |ale-vhdl-hdl-checker|
+
+
 ===============================================================================
 iverilog                                                 *ale-verilog-iverilog*
 
diff --git a/doc/ale-vhdl.txt b/doc/ale-vhdl.txt
index 3fea947d..c2870240 100644
--- a/doc/ale-vhdl.txt
+++ b/doc/ale-vhdl.txt
@@ -3,10 +3,10 @@ ALE VHDL Integration                                         *ale-vhdl-options*
 
 
 ===============================================================================
-ALE can use three different linters for VHDL:
+ALE can use four different linters for VHDL:
 
-  iverilog:
-    Using `iverilog -t null -Wall`
+  ghdl:
+    Using `ghdl --std=08`
 
   ModelSim/Questa
     Using `vcom -2008 -quiet -lint`
@@ -14,8 +14,15 @@ ALE can use three different linters for VHDL:
   Vivado
     Using `xvhdl --2008`
 
-Note all linters default to VHDL-2008 support. This, and other options, can be
-changed with each linter's respective option variable.
+  HDL Checker
+    Using `hdl_checker --lsp`
+
+===============================================================================
+General notes
+
+ghdl, ModelSim/Questa and Vivado linters default to VHDL-2008 support. This,
+and other options, can be changed with each linter's respective option
+variable.
 
 Linters/compilers that utilize a "work" directory for analyzing designs- such
 as ModelSim and Vivado- can be passed the location of these directories as
@@ -31,6 +38,10 @@ changing. This can happen in the form of hangs or crashes. To help prevent
 this when using these linters, it may help to run linting less frequently; for
 example, only when a file is saved.
 
+HDL Checker is an alternative for some of the issues described above. It wraps
+around ghdl, Vivado and ModelSim/Questa and, when using the latter, it can
+handle mixed language (VHDL, Verilog, SystemVerilog) designs.
+
 ===============================================================================
 ghdl                                                            *ale-vhdl-ghdl*
 
@@ -51,6 +62,60 @@ g:ale_vhdl_ghdl_options                               *g:ale_vhdl_ghdl_options*
 
 
 ===============================================================================
+hdl-checker                                              *ale-vhdl-hdl-checker*
+
+HDL Checker is a wrapper for VHDL/Verilg/SystemVerilog tools that aims to
+reduce the boilerplate code needed to set things up. It can automatically
+infer libraries for VHDL sources, determine the compilation order and provide
+some static checks.
+
+You can install it using pip:
+>
+  $ pip install hdl-checker
+
+`hdl-checker` will be run from a detected project root, determined by the
+following methods, in order:
+
+1. Find the first directory containing a configuration file (see
+   |g:ale_hdl_checker_config_file|)
+2. If no configuration file can be found, find the first directory containing
+   a folder named `'.git'
+3. If no such folder is found, use the directory of the current buffer
+
+
+g:ale_hdl_checker_executable
+                                                 *g:ale_hdl_checker_executable*
+                                                 *b:ale_hdl_checker_executable*
+  Type: |String|
+  Default: `'hdl_checker'`
+
+  This variable can be changed to the path to the 'hdl_checker' executable.
+
+
+g:ale_hdl_checker_options                           *g:ale_hdl_checker_options*
+                                                    *b:ale_hdl_checker_options*
+  Type: |String|
+  Default: `''`
+
+  This variable can be changed to modify the flags/options passed to the
+  'hdl_checker' server startup command.
+
+
+g:ale_hdl_checker_config_file                   *g:ale_hdl_checker_config_file*
+                                                *b:ale_hdl_checker_config_file*
+  Type: |String|
+  Default: `'.hdl_checker.config'` (Unix),
+           `'_hdl_checker.config'` (Windows)
+
+  This variable can be changed to modify the config file HDL Checker will try
+  to look for. It will also affect how the project's root directory is
+  determined (see |ale-vhdl-hdl-checker|).
+
+  More info on the configuration file format can be found at:
+  https://github.com/suoto/hdl_checker/wiki/Setting-up-a-project
+
+
+===============================================================================
 vcom                                                            *ale-vhdl-vcom*
 
 g:ale_vhdl_vcom_executable                         *g:ale_vhdl_vcom_executable*
diff --git a/doc/ale.txt b/doc/ale.txt
index c12d4208..e6b3e58d 100644
--- a/doc/ale.txt
+++ b/doc/ale.txt
@@ -2675,12 +2675,14 @@ documented in additional help files.
   vala....................................|ale-vala-options|
     uncrustify............................|ale-vala-uncrustify|
   verilog/systemverilog...................|ale-verilog-options|
+    hdl-checker...........................|ale-verilog-hdl-checker|
     iverilog..............................|ale-verilog-iverilog|
     verilator.............................|ale-verilog-verilator|
     vlog..................................|ale-verilog-vlog|
     xvlog.................................|ale-verilog-xvlog|
   vhdl....................................|ale-vhdl-options|
     ghdl..................................|ale-vhdl-ghdl|
+    hdl-checker...........................|ale-vhdl-hdl-checker|
     vcom..................................|ale-vhdl-vcom|
     xvhdl.................................|ale-vhdl-xvhdl|
   vim.....................................|ale-vim-options|