qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2021-11-02	Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into staging	Richard Henderson
2021-11-02	target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU	Philippe Mathieu-Daudé
2021-11-02	target/mips: Fix Loongson-3A4000 MSAIR config register	Philippe Mathieu-Daudé
2021-11-02	target/mips: Remove one MSA unnecessary decodetree overlap group	Philippe Mathieu-Daudé
2021-11-02	target/mips: Remove generic MSA opcode	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert CTCMSA opcode to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert CFCMSA opcode to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA MOVE.V opcode to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA COPY_U opcode to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA ELM instruction format to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA VEC instruction format to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA 2R instruction format to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA FILL opcode to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA 2RF instruction format to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA load/store instruction format to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA I8 instruction format to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA SHF opcode to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA BIT instruction format to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA I5 instruction format to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Convert MSA LDI opcode to decodetree	Philippe Mathieu-Daudé
2021-11-02	target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v	Philippe Mathieu-Daudé
2021-11-02	target/mips: Use enum definitions from CPUMIPSMSADataFormat enum	Philippe Mathieu-Daudé
2021-11-02	target/mips: Have check_msa_access() return a boolean	Philippe Mathieu-Daudé
2021-11-02	target/mips: Use dup_const() to simplify	Philippe Mathieu-Daudé
2021-11-02	target/mips: Adjust style in msa_translate_init()	Philippe Mathieu-Daudé
2021-11-02	target/mips: Fix MSA MSUBV.B opcode	Philippe Mathieu-Daudé
2021-11-02	target/mips: Fix MSA MADDV.B opcode	Philippe Mathieu-Daudé
2021-11-02	target/mips: Make mips_cpu_tlb_fill sysemu only	Richard Henderson
2021-10-18	target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()	Philippe Mathieu-Daudé
2021-10-18	target/mips: Fix DEXTRV_S.H DSP opcode	Philippe Mathieu-Daudé
2021-10-18	target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()	Philippe Mathieu-Daudé
2021-10-18	target/mips: Use explicit extract32() calls in gen_msa_i5()	Philippe Mathieu-Daudé
2021-10-18	target/mips: Use tcg_constant_i32() in gen_msa_3rf()	Philippe Mathieu-Daudé
2021-10-18	target/mips: Use tcg_constant_i32() in gen_msa_2r()	Philippe Mathieu-Daudé
2021-10-18	target/mips: Use tcg_constant_i32() in gen_msa_2rf()	Philippe Mathieu-Daudé
2021-10-18	target/mips: Use tcg_constant_i32() in gen_msa_elm_df()	Philippe Mathieu-Daudé
2021-10-18	target/mips: Remove unused register from MSA 2R/2RF instruction format	Philippe Mathieu-Daudé
2021-10-17	target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6	Philippe Mathieu-Daudé
2021-10-15	target/mips: Drop exit checks for singlestep_enabled	Richard Henderson
2021-10-15	target/mips: Fix single stepping	Richard Henderson
2021-10-13	target/mips: Use 8-byte memory ops for msa load/store	Richard Henderson
2021-10-13	target/mips: Use cpu_*_data_ra for msa load/store	Richard Henderson
2021-10-05	tcg: Rename TCGMemOpIdx to MemOpIdx	Richard Henderson