diff options
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 9 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 1 |
2 files changed, 10 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ef3314bce..31065ab9ad 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -209,6 +209,14 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } + +static void rv32_mullvad_picorv32_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, MXL_RV32, RVI | RVM | RVC); + qdev_prop_set_bit(DEVICE(obj), "mmu", false); + qdev_prop_set_bit(DEVICE(obj), "pmp", false); +} #endif static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -812,6 +820,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_MULLVAD_PICORV32, rv32_mullvad_picorv32_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dc10f27093..ef725d5be0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -45,6 +45,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_MULLVAD_PICORV32 RISCV_CPU_TYPE_NAME("mullvad-picorv32") #if defined(TARGET_RISCV32) # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 |