summaryrefslogtreecommitdiff
path: root/.github
AgeCommit message (Collapse)Author
2022-10-05ci/doc: build embassy-time too.Dario Nieuwenhuis
2022-10-03Use 1 thread in ci doc building.Dario Nieuwenhuis
2022-10-02Build docs in CIDario Nieuwenhuis
2022-08-22split `embassy-util` into `embassy-futures`, `embassy-sync`.Dario Nieuwenhuis
2022-07-29Split embassy crate into embassy-executor, embassy-util.Dario Nieuwenhuis
2022-04-08Update cargo-batch.Dario Nieuwenhuis
2022-03-14Tell bors to delete merged branchesGrant Miller
2022-02-12ci: add build with stable.Dario Nieuwenhuis
2022-02-11Update cargo-batch.Dario Nieuwenhuis
2021-12-06stm32: add gpio HIL testDario Nieuwenhuis
2021-11-24ci: do main build with fully generated stm32-metapac.Dario Nieuwenhuis
2021-11-22Faster CI with cargo-batchDario Nieuwenhuis
2021-11-07Merge #461bors[bot]
461: nrf: add initial nrf5340 support r=Dirbaio a=Dirbaio Thanks to `@diondokter's` work on DPPI this was quite easy! :) TODO: - [ ] Add config option to enable 128mhz - [ ] Add config option to unlock APPROTECT automatically. - [ ] Add a way to boot net (config option or API?) - [ ] Support WDT (there's WDT0, WDT1. Needs some refactor) - [ ] Support NVMC - [ ] Support TEMP Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-11-02Add stm32u5 examples to CI run.Bob McWhirter
2021-10-28nrf: add initial nrf5340 supportDario Nieuwenhuis
2021-10-27Merge #457bors[bot]
457: nrf91: support running in both S and NS mode. r=Dirbaio a=Dirbaio - Cargo feature `nrf9160` is now `nrf9160-s` or `nrf9160-ns` - "fake-PAC" renames everything appropriately so there's no need to spam cfg's everywhere. With `nrf9160-s` you can now run code without flashing any weird SPM/bootloader. Tested on nrf9160-dk. Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-10-26nrf91: support running in both S and NS mode.Dario Nieuwenhuis
2021-10-26Add stm32f7 to CIDario Nieuwenhuis
2021-10-13Merge #423bors[bot]
423: nRF9160 support r=Dirbaio a=diondokter - Created a chip file with all the peripherals, interrupts and peripheral implementations. - All peripherals now use an alias for the NS (non-secure) version of the nRF9160 version. - Implementations of peripherals that don't exist are ignored. - Most PPI functionality has been stubbed out because the nRF91 has the newer DPPI which is not compatible with the current API. (The channels are also set to not configurable, so they are kinda useless now, but in principle the stubs should never be called) Co-authored-by: Dion Dokter <dion@tweedegolf.com>
2021-10-13- Removed the enable assert from UARTE.Dion Dokter
- Added nRF9160 to CI.
2021-10-12Add borsDario Nieuwenhuis
2021-10-06Add matrix botDario Nieuwenhuis
2021-09-28Initial STM32F1 family support with two examples for STM32F103C8 (Blue Pill)Mariusz Ryndzionek
2021-09-21Support for STM32L1Ulf Lilleengen
* Add RCC * Fix more issues with dash in chip names * Update stm32-data version * Add blinky and spi example
2021-09-13Add WASM support for executorUlf Lilleengen
* Adds an executor for WASM runtimes based on wasm_bindgen. * Add time driver based on JS time handling. * Add example that can run in browser locally. * Update to critical-section version that supports 'std' flag
2021-08-20stm32: add G0 to CiDario Nieuwenhuis
2021-08-18Add STM32WL55 examples to CI (#361)Ulf Lilleengen
* Add STM32WL55 examples to CI and fix warnings
2021-08-05time: replace dyn clock/alarm with a global Driver traitDario Nieuwenhuis
2021-08-04ci: rustfmt check all .rs filesDario Nieuwenhuis
The old script was missing many .rs files that were not enabled due to cfg's.
2021-07-28Revert "Optimize CI"Bob McWhirter
This reverts commit fe58e9541d97d16d39534cb8d38c68c61b6f8726.
2021-07-24Optimize CIDario Nieuwenhuis
2021-07-15stm32: Add F0 exampleThales Fragoso
2021-07-13Fix "can't find crate for std" for stm32-metapac-gen deps.Dario Nieuwenhuis
2021-07-06Add tests to our CIhuntc
Also found some doctests that were failing
2021-07-05Deny warnings in CIDario Nieuwenhuis
2021-06-16Add support for generating PAC for dual coresUlf Lilleengen
* Chips that have multiple cores will be exposed as chipname_corename, i.e. stm32wl55jc_cm4 * Chips that have single cores will use the chip family as feature name and pick the first and only core from the list * Add support for stm32wl55 chip family
2021-06-12Add STM32WB55 examples to CI, fix example crate nameDominik Boehi
2021-06-10Run metapac full gen in CiDario Nieuwenhuis
2021-06-09Add examples for STM32L0Ulf Lilleengen
2021-06-08Initial swag at h7 examples.Bob McWhirter
2021-06-08Add to GHA.Bob McWhirter
2021-06-02Move examples to a subdirectoryDario Nieuwenhuis
2021-05-31Really checkout submodules in CIDario Nieuwenhuis
2021-05-31Checkout submodules in ciDario Nieuwenhuis
2021-05-28net: add ciDario Nieuwenhuis
2021-05-21Add stm32l0 to CIDario Nieuwenhuis
2021-05-19Build with executor-agnostic in CIDario Nieuwenhuis
2021-05-17Add more chips to CIDario Nieuwenhuis
2021-05-17Add more chips to CIDario Nieuwenhuis
2021-05-17stm32: fix build, add ciDario Nieuwenhuis
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 17:42:14 +0000