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authorDario Nieuwenhuis <dirbaio@dirbaio.net>2022-03-15 00:46:18 +0100
committerDario Nieuwenhuis <dirbaio@dirbaio.net>2022-03-15 02:14:24 +0100
commit06f35c25176795c8e856ea7b41a52dba4b160f66 (patch)
tree1b1ed6e1d85012e4e0b13ef318d18c0accb17857 /tests
parent306110f56e4614cc51f6c3d3e9ff96b5fe2ced6f (diff)
downloadembassy-06f35c25176795c8e856ea7b41a52dba4b160f66.zip
stm32/spi: more exhaustive test.
Diffstat (limited to 'tests')
-rw-r--r--tests/stm32/src/bin/spi.rs15
-rw-r--r--tests/stm32/src/bin/spi_dma.rs12
2 files changed, 27 insertions, 0 deletions
diff --git a/tests/stm32/src/bin/spi.rs b/tests/stm32/src/bin/spi.rs
index 47d0017a..6151058b 100644
--- a/tests/stm32/src/bin/spi.rs
+++ b/tests/stm32/src/bin/spi.rs
@@ -37,9 +37,24 @@ async fn main(_spawner: Spawner, p: Peripherals) {
// Arduino pins D11 and D12 (MOSI-MISO) are connected together with a 1K resistor.
// so we should get the data we sent back.
let mut buf = data;
+ spi.blocking_transfer(&mut buf, &data).unwrap();
+ assert_eq!(buf, data);
+
spi.blocking_transfer_in_place(&mut buf).unwrap();
assert_eq!(buf, data);
+ // Check read/write don't hang. We can't check they transfer the right data
+ // without fancier test mechanisms.
+ spi.blocking_write(&buf).unwrap();
+ spi.blocking_read(&mut buf).unwrap();
+ spi.blocking_write(&buf).unwrap();
+ spi.blocking_read(&mut buf).unwrap();
+ spi.blocking_write(&buf).unwrap();
+
+ // Check transfer doesn't break after having done a write, due to garbage in the FIFO
+ spi.blocking_transfer(&mut buf, &data).unwrap();
+ assert_eq!(buf, data);
+
info!("Test OK");
cortex_m::asm::bkpt();
}
diff --git a/tests/stm32/src/bin/spi_dma.rs b/tests/stm32/src/bin/spi_dma.rs
index ce80bde7..67785778 100644
--- a/tests/stm32/src/bin/spi_dma.rs
+++ b/tests/stm32/src/bin/spi_dma.rs
@@ -50,6 +50,18 @@ async fn main(_spawner: Spawner, p: Peripherals) {
spi.transfer_in_place(&mut buf).await.unwrap();
assert_eq!(buf, data);
+ // Check read/write don't hang. We can't check they transfer the right data
+ // without fancier test mechanisms.
+ spi.write(&buf).await.unwrap();
+ spi.read(&mut buf).await.unwrap();
+ spi.write(&buf).await.unwrap();
+ spi.read(&mut buf).await.unwrap();
+ spi.write(&buf).await.unwrap();
+
+ // Check transfer doesn't break after having done a write, due to garbage in the FIFO
+ spi.transfer(&mut buf, &data).await.unwrap();
+ assert_eq!(buf, data);
+
info!("Test OK");
cortex_m::asm::bkpt();
}