Update stm32-data

2 files changed, 15 insertions, 28 deletions

diff --git a/stm32-metapac-gen/src/data.rs b/stm32-metapac-gen/src/data.rs
index 2fa4c4b0..56a121ff 100644
--- a/stm32-metapac-gen/src/data.rs
+++ b/stm32-metapac-gen/src/data.rs
@@ -1,5 +1,4 @@
 use serde::Deserialize;
-use std::collections::HashMap;
 
 #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
 pub struct Chip {
@@ -7,21 +6,24 @@ pub struct Chip {
     pub family: String,
     pub line: String,
     pub cores: Vec<Core>,
-    pub flash: Memory,
-    pub ram: Memory,
+    pub memory: Vec<MemoryRegion>,
     pub packages: Vec<Package>,
 }
 
 #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
-pub struct Memory {
-    pub bytes: u32,
-    pub regions: HashMap<String, MemoryRegion>,
+pub struct MemoryRegion {
+    pub name: String,
+    pub kind: MemoryRegionKind,
+    pub address: u32,
+    pub size: u32,
 }
 
 #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
-pub struct MemoryRegion {
-    pub base: u32,
-    pub bytes: Option<u32>,
+pub enum MemoryRegionKind {
+    #[serde(rename = "flash")]
+    Flash,
+    #[serde(rename = "ram")]
+    Ram,
 }
 
 #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
diff --git a/stm32-metapac-gen/src/lib.rs b/stm32-metapac-gen/src/lib.rs
index a4d4de5f..07de4f1e 100644
--- a/stm32-metapac-gen/src/lib.rs
+++ b/stm32-metapac-gen/src/lib.rs
@@ -587,35 +587,20 @@ fn bytes_find(haystack: &[u8], needle: &[u8]) -> Option<usize> {
 fn gen_memory_x(out_dir: &PathBuf, chip: &Chip) {
     let mut memory_x = String::new();
 
-    let flash_bytes = chip
-        .flash
-        .regions
-        .get("BANK_1")
-        .unwrap()
-        .bytes
-        .unwrap_or(chip.flash.bytes);
-    let flash_origin = chip.flash.regions.get("BANK_1").unwrap().base;
-
-    let ram_bytes = chip
-        .ram
-        .regions
-        .get("SRAM")
-        .unwrap()
-        .bytes
-        .unwrap_or(chip.ram.bytes);
-    let ram_origin = chip.ram.regions.get("SRAM").unwrap().base;
+    let flash = chip.memory.iter().find(|r| r.name == "BANK_1").unwrap();
+    let ram = chip.memory.iter().find(|r| r.name == "SRAM").unwrap();
 
     write!(memory_x, "MEMORY\n{{\n").unwrap();
     write!(
         memory_x,
         "    FLASH : ORIGIN = 0x{:x}, LENGTH = {}\n",
-        flash_origin, flash_bytes
+        flash.address, flash.size,
     )
     .unwrap();
     write!(
         memory_x,
         "    RAM : ORIGIN = 0x{:x}, LENGTH = {}\n",
-        ram_origin, ram_bytes
+        ram.address, ram.size,
     )
     .unwrap();
     write!(memory_x, "}}").unwrap();