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authorMatous Hybl <hyblmatous@gmail.com>2022-10-18 22:42:02 +0200
committerMatous Hybl <hyblmatous@gmail.com>2022-10-18 22:42:02 +0200
commit6c5d81ada52bfac1592c7be025038a3eea3acc42 (patch)
tree7f41b9583e614bc036f29605e1c15478968dcf8d /embassy-stm32
parent18453ee64c7d1b397aa96cb322cedee6166b4602 (diff)
downloadembassy-6c5d81ada52bfac1592c7be025038a3eea3acc42.zip
Add memory barriers to H7 flash driver to mitigate PGSERR errors
The stm32h7xx-hal uses only the ordering barrier, while the CubeMX uses the DSB and ISB instructions, to be on the safe side, both are used here.
Diffstat (limited to 'embassy-stm32')
-rw-r--r--embassy-stm32/src/flash/h7.rs8
1 files changed, 8 insertions, 0 deletions
diff --git a/embassy-stm32/src/flash/h7.rs b/embassy-stm32/src/flash/h7.rs
index 7ce0ac77..3f2129de 100644
--- a/embassy-stm32/src/flash/h7.rs
+++ b/embassy-stm32/src/flash/h7.rs
@@ -39,6 +39,10 @@ pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error
w.set_psize(2); // 32 bits at once
});
+ cortex_m::asm::isb();
+ cortex_m::asm::dsb();
+ atomic_polyfill::fence(atomic_polyfill::Ordering::SeqCst);
+
let ret = {
let mut ret: Result<(), Error> = Ok(());
let mut offset = offset;
@@ -64,6 +68,10 @@ pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error
bank.cr().write(|w| w.set_pg(false));
+ cortex_m::asm::isb();
+ cortex_m::asm::dsb();
+ atomic_polyfill::fence(atomic_polyfill::Ordering::SeqCst);
+
ret
}