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authorMathias <mk@blackbird.online>2022-09-28 05:19:43 +0200
committerMathias <mk@blackbird.online>2022-09-28 05:19:43 +0200
commit823bd714fb6da94cf3b31c2066c398207228b4c6 (patch)
treeada80c9c3af0193e9c3604c072356c281541b886
parent9bb43ffe9adddb3497bb08d0730635fbd66cff94 (diff)
downloadembassy-823bd714fb6da94cf3b31c2066c398207228b4c6.zip
Add E-H1 uart blocking & nb implementation
-rw-r--r--embassy-stm32/src/usart/mod.rs73
1 files changed, 73 insertions, 0 deletions
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 6c266874..5ee09934 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -359,6 +359,79 @@ mod eh1 {
impl<'d, T: BasicInstance, RxDma> embedded_hal_1::serial::ErrorType for UartRx<'d, T, RxDma> {
type Error = Error;
}
+
+
+ impl<'d, T: BasicInstance, RxDma> embedded_hal_1::serial::nb::Read for UartRx<'d, T, RxDma> {
+ fn read(&mut self) -> nb::Result<u8, Self::Error> {
+ let r = T::regs();
+ unsafe {
+ let sr = sr(r).read();
+ if sr.pe() {
+ rdr(r).read_volatile();
+ Err(nb::Error::Other(Error::Parity))
+ } else if sr.fe() {
+ rdr(r).read_volatile();
+ Err(nb::Error::Other(Error::Framing))
+ } else if sr.ne() {
+ rdr(r).read_volatile();
+ Err(nb::Error::Other(Error::Noise))
+ } else if sr.ore() {
+ rdr(r).read_volatile();
+ Err(nb::Error::Other(Error::Overrun))
+ } else if sr.rxne() {
+ Ok(rdr(r).read_volatile())
+ } else {
+ Err(nb::Error::WouldBlock)
+ }
+ }
+ }
+ }
+
+ impl<'d, T: BasicInstance, TxDma> embedded_hal_1::serial::blocking::Write for UartTx<'d, T, TxDma> {
+ fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
+ self.blocking_write(buffer)
+ }
+
+ fn flush(&mut self) -> Result<(), Self::Error> {
+ self.blocking_flush()
+ }
+ }
+
+ impl<'d, T: BasicInstance, TxDma> embedded_hal_1::serial::nb::Write for UartTx<'d, T, TxDma> {
+ fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
+ self.blocking_write(&[char]).map_err(nb::Error::Other)
+ }
+
+ fn flush(&mut self) -> nb::Result<(), Self::Error> {
+ self.blocking_flush().map_err(nb::Error::Other)
+ }
+ }
+
+ impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_1::serial::nb::Read for Uart<'d, T, TxDma, RxDma> {
+ fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
+ embedded_hal_02::serial::Read::read(&mut self.rx)
+ }
+ }
+
+ impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_1::serial::blocking::Write for Uart<'d, T, TxDma, RxDma> {
+ fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
+ self.blocking_write(buffer)
+ }
+
+ fn flush(&mut self) -> Result<(), Self::Error> {
+ self.blocking_flush()
+ }
+ }
+
+ impl<'d, T: BasicInstance, TxDma, RxDma> embedded_hal_1::serial::nb::Write for Uart<'d, T, TxDma, RxDma> {
+ fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
+ self.blocking_write(&[char]).map_err(nb::Error::Other)
+ }
+
+ fn flush(&mut self) -> nb::Result<(), Self::Error> {
+ self.blocking_flush().map_err(nb::Error::Other)
+ }
+ }
}
#[cfg(all(