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-rw-r--r--Userland/DevTools/UserspaceEmulator/SoftCPU.cpp9
-rw-r--r--Userland/DevTools/UserspaceEmulator/SoftCPU.h6
-rw-r--r--Userland/Libraries/LibX86/Instruction.cpp23
-rw-r--r--Userland/Libraries/LibX86/Instruction.h2
-rw-r--r--Userland/Libraries/LibX86/Interpreter.h6
5 files changed, 39 insertions, 7 deletions
diff --git a/Userland/DevTools/UserspaceEmulator/SoftCPU.cpp b/Userland/DevTools/UserspaceEmulator/SoftCPU.cpp
index 784311d8cd..6063d812ef 100644
--- a/Userland/DevTools/UserspaceEmulator/SoftCPU.cpp
+++ b/Userland/DevTools/UserspaceEmulator/SoftCPU.cpp
@@ -3528,9 +3528,13 @@ DEFINE_GENERIC_INSN_HANDLERS(AND, op_and, true, false, false)
DEFINE_GENERIC_INSN_HANDLERS(CMP, op_sub, false, false, false)
DEFINE_GENERIC_INSN_HANDLERS_PARTIAL(TEST, op_and, false, false, false)
-void SoftCPU::MOVQ_mm1_mm2m64(const X86::Instruction&) { TODO_INSN(); }
+void SoftCPU::MOVQ_mm1_mm2m64(const X86::Instruction&) { TODO_INSN(); };
+void SoftCPU::MOVQ_mm1m64_mm2(const X86::Instruction&) { TODO_INSN(); };
+void SoftCPU::MOVD_mm1_rm32(const X86::Instruction&) { TODO_INSN(); };
+void SoftCPU::MOVQ_mm1_rm64(const X86::Instruction&) { TODO_INSN(); }; // long mode
+void SoftCPU::MOVD_rm32_mm2(const X86::Instruction&) { TODO_INSN(); };
+void SoftCPU::MOVQ_rm64_mm2(const X86::Instruction&) { TODO_INSN(); }; // long mode
void SoftCPU::EMMS(const X86::Instruction&) { TODO_INSN(); }
-void SoftCPU::MOVQ_mm1_m64_mm2(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::wrap_0xC0(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::wrap_0xC1_16(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::wrap_0xC1_32(const X86::Instruction&) { TODO_INSN(); }
@@ -3540,4 +3544,5 @@ void SoftCPU::wrap_0xD1_32(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::wrap_0xD2(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::wrap_0xD3_16(const X86::Instruction&) { TODO_INSN(); }
void SoftCPU::wrap_0xD3_32(const X86::Instruction&) { TODO_INSN(); }
+
}
diff --git a/Userland/DevTools/UserspaceEmulator/SoftCPU.h b/Userland/DevTools/UserspaceEmulator/SoftCPU.h
index 3d5f287e7f..601d7f82c0 100644
--- a/Userland/DevTools/UserspaceEmulator/SoftCPU.h
+++ b/Userland/DevTools/UserspaceEmulator/SoftCPU.h
@@ -1094,8 +1094,12 @@ private:
virtual void XOR_reg32_RM32(const X86::Instruction&) override;
virtual void XOR_reg8_RM8(const X86::Instruction&) override;
virtual void MOVQ_mm1_mm2m64(const X86::Instruction&) override;
+ virtual void MOVQ_mm1m64_mm2(const X86::Instruction&) override;
+ virtual void MOVD_mm1_rm32(const X86::Instruction&) override;
+ virtual void MOVQ_mm1_rm64(const X86::Instruction&) override; // long mode
+ virtual void MOVD_rm32_mm2(const X86::Instruction&) override;
+ virtual void MOVQ_rm64_mm2(const X86::Instruction&) override; // long mode
virtual void EMMS(const X86::Instruction&) override;
- virtual void MOVQ_mm1_m64_mm2(const X86::Instruction&) override;
virtual void wrap_0xC0(const X86::Instruction&) override;
virtual void wrap_0xC1_16(const X86::Instruction&) override;
virtual void wrap_0xC1_32(const X86::Instruction&) override;
diff --git a/Userland/Libraries/LibX86/Instruction.cpp b/Userland/Libraries/LibX86/Instruction.cpp
index aba6379e6e..57328b6e27 100644
--- a/Userland/Libraries/LibX86/Instruction.cpp
+++ b/Userland/Libraries/LibX86/Instruction.cpp
@@ -142,6 +142,8 @@ static void build(InstructionDescriptor* table, u8 op, const char* mnemonic, Ins
case OP_CR_reg32:
case OP_reg16_RM8:
case OP_reg32_RM8:
+ case OP_mm1_rm32:
+ case OP_rm32_mm2:
case OP_mm1_mm2m64:
case OP_mm1_mm2m32:
case OP_mm1m64_mm2:
@@ -812,6 +814,7 @@ static void build_slash_reg(u8 op, u8 slash, const char* mnemonic, InstructionFo
build_0f(0x69, "PUNPCKHWD", OP_mm1_mm2m64, &Interpreter::PUNPCKHWD_mm1_mm2m64);
build_0f(0x6A, "PUNPCKHDQ", OP_mm1_mm2m64, &Interpreter::PUNPCKHDQ_mm1_mm2m64);
build_0f(0x6B, "PACKSSDW", OP_mm1_mm2m64, &Interpreter::PACKSSDW_mm1_mm2m64);
+ build_0f(0x6E, "MOVD", OP_mm1_rm32, &Interpreter::MOVD_mm1_rm32);
build_0f(0x6F, "MOVQ", OP_mm1_mm2m64, &Interpreter::MOVQ_mm1_mm2m64);
build_0f_slash(0x71, 2, "PSRLW", OP_mm1_imm8, &Interpreter::PSRLW_mm1_mm2m64);
@@ -829,7 +832,8 @@ static void build_slash_reg(u8 op, u8 slash, const char* mnemonic, InstructionFo
build_0f(0x76, "PCMPEQD", OP_mm1_mm2m64, &Interpreter::PCMPEQD_mm1_mm2m64);
build_0f(0x75, "PCMPEQW", OP_mm1_mm2m64, &Interpreter::PCMPEQW_mm1_mm2m64);
build_0f(0x77, "EMMS", OP, &Interpreter::EMMS);
- build_0f(0x7F, "MOVQ", OP_mm1m64_mm2, &Interpreter::MOVQ_mm1_m64_mm2);
+ build_0f(0x7E, "MOVD", OP_rm32_mm2, &Interpreter::MOVD_rm32_mm2);
+ build_0f(0x7F, "MOVQ", OP_mm1m64_mm2, &Interpreter::MOVQ_mm1m64_mm2);
build_0f(0x80, "JO", OP_NEAR_imm, &Interpreter::Jcc_NEAR_imm);
build_0f(0x81, "JNO", OP_NEAR_imm, &Interpreter::Jcc_NEAR_imm);
@@ -1319,6 +1323,7 @@ void Instruction::to_string_internal(StringBuilder& builder, u32 origin, const S
auto append_relative_imm32 = [&] { formatted_address(origin + 5, x32, i32(imm32())); };
auto append_mm = [&] { builder.appendff("mm{}", register_index()); };
+ auto append_mmrm32 = [&] { builder.append(m_modrm.to_string_mm(*this)); };
auto append_mmrm64 = [&] { builder.append(m_modrm.to_string_mm(*this)); };
auto append = [&](auto& content) { builder.append(content); };
@@ -1846,8 +1851,20 @@ void Instruction::to_string_internal(StringBuilder& builder, u32 origin, const S
append_mnemonic_space();
append_mm();
append(", ");
+ append_mmrm32();
+ break;
+ case OP_mm1_rm32:
+ append_mnemonic_space();
+ append_mm();
+ append(", ");
append_rm32();
break;
+ case OP_rm32_mm2:
+ append_mnemonic_space();
+ append_rm32();
+ append(", ");
+ append_mm();
+ break;
case OP_mm1_mm2m64:
append_mnemonic_space();
append_mm();
@@ -1856,9 +1873,9 @@ void Instruction::to_string_internal(StringBuilder& builder, u32 origin, const S
break;
case OP_mm1m64_mm2:
append_mnemonic_space();
- append_mm();
- append(", ");
append_mmrm64();
+ append(", ");
+ append_mm();
break;
case InstructionPrefix:
append_mnemonic();
diff --git a/Userland/Libraries/LibX86/Instruction.h b/Userland/Libraries/LibX86/Instruction.h
index e515165cd2..e72599ddee 100644
--- a/Userland/Libraries/LibX86/Instruction.h
+++ b/Userland/Libraries/LibX86/Instruction.h
@@ -103,6 +103,8 @@ enum InstructionFormat {
OP_RM32_reg32_imm8,
OP_RM16_reg16_CL,
OP_RM32_reg32_CL,
+ OP_mm1_rm32,
+ OP_rm32_mm2,
OP_mm1_mm2m64,
OP_mm1_mm2m32,
OP_mm1_imm8,
diff --git a/Userland/Libraries/LibX86/Interpreter.h b/Userland/Libraries/LibX86/Interpreter.h
index b451acd777..1023a7e65b 100644
--- a/Userland/Libraries/LibX86/Interpreter.h
+++ b/Userland/Libraries/LibX86/Interpreter.h
@@ -641,8 +641,12 @@ public:
virtual void XOR_reg32_RM32(const Instruction&) = 0;
virtual void XOR_reg8_RM8(const Instruction&) = 0;
virtual void MOVQ_mm1_mm2m64(const Instruction&) = 0;
+ virtual void MOVQ_mm1m64_mm2(const Instruction&) = 0;
+ virtual void MOVD_mm1_rm32(const Instruction&) = 0;
+ virtual void MOVQ_mm1_rm64(const Instruction&) = 0; // long mode
+ virtual void MOVD_rm32_mm2(const Instruction&) = 0;
+ virtual void MOVQ_rm64_mm2(const Instruction&) = 0; // long mode
virtual void EMMS(const Instruction&) = 0;
- virtual void MOVQ_mm1_m64_mm2(const Instruction&) = 0;
virtual void wrap_0xC0(const Instruction&) = 0;
virtual void wrap_0xC1_16(const Instruction&) = 0;
virtual void wrap_0xC1_32(const Instruction&) = 0;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 11:45:00 +0000