diff options
| author | Simon Wanner <skyrising@pvpctutorials.de> | 2022-03-25 00:08:40 +0100 |
|---|---|---|
| committer | Andreas Kling <kling@serenityos.org> | 2022-11-26 12:50:38 +0100 |
| commit | 06ece474e96df24d6126bab2fdac7822c267ff62 (patch) | |
| tree | e9a9a05908e4ac41271de7b5519c541af04d3b23 /Userland/DevTools/UserspaceEmulator | |
| parent | a7268c3c742191cbc13762f5a71af2ffe7e4b6bc (diff) | |
| download | serenity-06ece474e96df24d6126bab2fdac7822c267ff62.zip | |
LibX86: Add {Address,Operand}Size::Size64
For now the opcode tables for OperandSize::Size64 are empty
Diffstat (limited to 'Userland/DevTools/UserspaceEmulator')
| -rw-r--r-- | Userland/DevTools/UserspaceEmulator/SoftCPU.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/Userland/DevTools/UserspaceEmulator/SoftCPU.h b/Userland/DevTools/UserspaceEmulator/SoftCPU.h index 16982e6337..2206aae73d 100644 --- a/Userland/DevTools/UserspaceEmulator/SoftCPU.h +++ b/Userland/DevTools/UserspaceEmulator/SoftCPU.h @@ -106,8 +106,9 @@ public: return m_gpr[X86::RegisterEDX].reference_to<&PartAddressableRegister::low_u8>(); case X86::RegisterDH: return m_gpr[X86::RegisterEDX].reference_to<&PartAddressableRegister::high_u8>(); + default: + VERIFY_NOT_REACHED(); } - VERIFY_NOT_REACHED(); } ValueWithShadow<u8> const_gpr8(X86::RegisterIndex8 reg) const @@ -129,8 +130,9 @@ public: return m_gpr[X86::RegisterEDX].slice<&PartAddressableRegister::low_u8>(); case X86::RegisterDH: return m_gpr[X86::RegisterEDX].slice<&PartAddressableRegister::high_u8>(); + default: + VERIFY_NOT_REACHED(); } - VERIFY_NOT_REACHED(); } ValueWithShadow<u16> const_gpr16(X86::RegisterIndex16 reg) const @@ -211,8 +213,9 @@ public: case X86::AddressSize::Size16: set_cx(ValueWithShadow<u16>(cx().value() - 1, cx().shadow())); return cx().value() == 0; + default: + VERIFY_NOT_REACHED(); } - VERIFY_NOT_REACHED(); } ALWAYS_INLINE void step_source_index(X86::AddressSize address_size, u32 step) |