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authorLiav A <liavalb@gmail.com>2021-03-27 21:44:25 +0300
committerAndreas Kling <kling@serenityos.org>2021-04-03 11:57:23 +0200
commit2718d7c74cc7a3c5b125fe1ec89ab189547b1dd8 (patch)
treea54189ad2a63e3df708cb34d975245170248d194 /Kernel/Storage/IDEChannel.cpp
parent627cfe017c34ccd08a4a047a5548703b66d447cd (diff)
downloadserenity-2718d7c74cc7a3c5b125fe1ec89ab189547b1dd8.zip
Kernel/Storage: Add support for IDE controllers in PCI native mode
Also handle native and compatibility channel modes together, so if only one IDE channel was set to work on PCI native mode, we need to handle it separately, so the other channel continue to operate with the legacy IO ports and interrupt line.
Diffstat (limited to 'Kernel/Storage/IDEChannel.cpp')
-rw-r--r--Kernel/Storage/IDEChannel.cpp32
1 files changed, 24 insertions, 8 deletions
diff --git a/Kernel/Storage/IDEChannel.cpp b/Kernel/Storage/IDEChannel.cpp
index 52e324a8d3..f8b7418130 100644
--- a/Kernel/Storage/IDEChannel.cpp
+++ b/Kernel/Storage/IDEChannel.cpp
@@ -49,6 +49,11 @@ UNMAP_AFTER_INIT NonnullRefPtr<IDEChannel> IDEChannel::create(const IDEControlle
return adopt(*new IDEChannel(controller, io_group, type));
}
+UNMAP_AFTER_INIT NonnullRefPtr<IDEChannel> IDEChannel::create(const IDEController& controller, u8 irq, IOAddressGroup io_group, ChannelType type)
+{
+ return adopt(*new IDEChannel(controller, irq, io_group, type));
+}
+
RefPtr<StorageDevice> IDEChannel::master_device() const
{
return m_master;
@@ -59,16 +64,9 @@ RefPtr<StorageDevice> IDEChannel::slave_device() const
return m_slave;
}
-UNMAP_AFTER_INIT IDEChannel::IDEChannel(const IDEController& controller, IOAddressGroup io_group, ChannelType type)
- : IRQHandler(type == ChannelType::Primary ? PATA_PRIMARY_IRQ : PATA_SECONDARY_IRQ)
- , m_channel_type(type)
- , m_io_group(io_group)
- , m_parent_controller(controller)
+UNMAP_AFTER_INIT void IDEChannel::initialize()
{
disable_irq();
-
- // FIXME: The device may not be capable of DMA.
-
dbgln_if(PATA_DEBUG, "IDEChannel: {} IO base: {}", channel_type_string(), m_io_group.io_base());
dbgln_if(PATA_DEBUG, "IDEChannel: {} control base: {}", channel_type_string(), m_io_group.control_base());
if (m_io_group.bus_master_base().has_value())
@@ -83,6 +81,24 @@ UNMAP_AFTER_INIT IDEChannel::IDEChannel(const IDEController& controller, IOAddre
clear_pending_interrupts();
}
+UNMAP_AFTER_INIT IDEChannel::IDEChannel(const IDEController& controller, u8 irq, IOAddressGroup io_group, ChannelType type)
+ : IRQHandler(irq)
+ , m_channel_type(type)
+ , m_io_group(io_group)
+ , m_parent_controller(controller)
+{
+ initialize();
+}
+
+UNMAP_AFTER_INIT IDEChannel::IDEChannel(const IDEController& controller, IOAddressGroup io_group, ChannelType type)
+ : IRQHandler(type == ChannelType::Primary ? PATA_PRIMARY_IRQ : PATA_SECONDARY_IRQ)
+ , m_channel_type(type)
+ , m_io_group(io_group)
+ , m_parent_controller(controller)
+{
+ initialize();
+}
+
void IDEChannel::clear_pending_interrupts() const
{
m_io_group.io_base().offset(ATA_REG_STATUS).in<u8>();