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authorAndreas Kling <awesomekling@gmail.com>2019-06-07 11:43:58 +0200
committerAndreas Kling <awesomekling@gmail.com>2019-06-07 11:43:58 +0200
commitbc951ca565d137b2d1bd158e5473bd42cf568d10 (patch)
treed726fbd8f661b52a7c3d549a5f08f98e0443ca0c /Kernel/Net/E1000NetworkAdapter.cpp
parent98eeb8f22df509b2a711de0e4a01660b6646f229 (diff)
downloadserenity-bc951ca565d137b2d1bd158e5473bd42cf568d10.zip
Kernel: Run clang-format on everything.
Diffstat (limited to 'Kernel/Net/E1000NetworkAdapter.cpp')
-rw-r--r--Kernel/Net/E1000NetworkAdapter.cpp142
1 files changed, 71 insertions, 71 deletions
diff --git a/Kernel/Net/E1000NetworkAdapter.cpp b/Kernel/Net/E1000NetworkAdapter.cpp
index b73ddc70e2..a57e3bf97e 100644
--- a/Kernel/Net/E1000NetworkAdapter.cpp
+++ b/Kernel/Net/E1000NetworkAdapter.cpp
@@ -1,90 +1,90 @@
+#include <Kernel/IO.h>
#include <Kernel/Net/E1000NetworkAdapter.h>
#include <Kernel/PCI.h>
-#include <Kernel/IO.h>
-#define REG_CTRL 0x0000
-#define REG_STATUS 0x0008
-#define REG_EEPROM 0x0014
-#define REG_CTRL_EXT 0x0018
-#define REG_IMASK 0x00D0
-#define REG_RCTRL 0x0100
-#define REG_RXDESCLO 0x2800
-#define REG_RXDESCHI 0x2804
-#define REG_RXDESCLEN 0x2808
-#define REG_RXDESCHEAD 0x2810
-#define REG_RXDESCTAIL 0x2818
-#define REG_TCTRL 0x0400
-#define REG_TXDESCLO 0x3800
-#define REG_TXDESCHI 0x3804
-#define REG_TXDESCLEN 0x3808
-#define REG_TXDESCHEAD 0x3810
-#define REG_TXDESCTAIL 0x3818
-#define REG_RDTR 0x2820 // RX Delay Timer Register
-#define REG_RXDCTL 0x3828 // RX Descriptor Control
-#define REG_RADV 0x282C // RX Int. Absolute Delay Timer
-#define REG_RSRPD 0x2C00 // RX Small Packet Detect Interrupt
-#define REG_TIPG 0x0410 // Transmit Inter Packet Gap
-#define ECTRL_SLU 0x40 //set link up
-#define RCTL_EN (1 << 1) // Receiver Enable
-#define RCTL_SBP (1 << 2) // Store Bad Packets
-#define RCTL_UPE (1 << 3) // Unicast Promiscuous Enabled
-#define RCTL_MPE (1 << 4) // Multicast Promiscuous Enabled
-#define RCTL_LPE (1 << 5) // Long Packet Reception Enable
-#define RCTL_LBM_NONE (0 << 6) // No Loopback
-#define RCTL_LBM_PHY (3 << 6) // PHY or external SerDesc loopback
-#define RTCL_RDMTS_HALF (0 << 8) // Free Buffer Threshold is 1/2 of RDLEN
-#define RTCL_RDMTS_QUARTER (1 << 8) // Free Buffer Threshold is 1/4 of RDLEN
-#define RTCL_RDMTS_EIGHTH (2 << 8) // Free Buffer Threshold is 1/8 of RDLEN
-#define RCTL_MO_36 (0 << 12) // Multicast Offset - bits 47:36
-#define RCTL_MO_35 (1 << 12) // Multicast Offset - bits 46:35
-#define RCTL_MO_34 (2 << 12) // Multicast Offset - bits 45:34
-#define RCTL_MO_32 (3 << 12) // Multicast Offset - bits 43:32
-#define RCTL_BAM (1 << 15) // Broadcast Accept Mode
-#define RCTL_VFE (1 << 18) // VLAN Filter Enable
-#define RCTL_CFIEN (1 << 19) // Canonical Form Indicator Enable
-#define RCTL_CFI (1 << 20) // Canonical Form Indicator Bit Value
-#define RCTL_DPF (1 << 22) // Discard Pause Frames
-#define RCTL_PMCF (1 << 23) // Pass MAC Control Frames
-#define RCTL_SECRC (1 << 26) // Strip Ethernet CRC
+#define REG_CTRL 0x0000
+#define REG_STATUS 0x0008
+#define REG_EEPROM 0x0014
+#define REG_CTRL_EXT 0x0018
+#define REG_IMASK 0x00D0
+#define REG_RCTRL 0x0100
+#define REG_RXDESCLO 0x2800
+#define REG_RXDESCHI 0x2804
+#define REG_RXDESCLEN 0x2808
+#define REG_RXDESCHEAD 0x2810
+#define REG_RXDESCTAIL 0x2818
+#define REG_TCTRL 0x0400
+#define REG_TXDESCLO 0x3800
+#define REG_TXDESCHI 0x3804
+#define REG_TXDESCLEN 0x3808
+#define REG_TXDESCHEAD 0x3810
+#define REG_TXDESCTAIL 0x3818
+#define REG_RDTR 0x2820 // RX Delay Timer Register
+#define REG_RXDCTL 0x3828 // RX Descriptor Control
+#define REG_RADV 0x282C // RX Int. Absolute Delay Timer
+#define REG_RSRPD 0x2C00 // RX Small Packet Detect Interrupt
+#define REG_TIPG 0x0410 // Transmit Inter Packet Gap
+#define ECTRL_SLU 0x40 //set link up
+#define RCTL_EN (1 << 1) // Receiver Enable
+#define RCTL_SBP (1 << 2) // Store Bad Packets
+#define RCTL_UPE (1 << 3) // Unicast Promiscuous Enabled
+#define RCTL_MPE (1 << 4) // Multicast Promiscuous Enabled
+#define RCTL_LPE (1 << 5) // Long Packet Reception Enable
+#define RCTL_LBM_NONE (0 << 6) // No Loopback
+#define RCTL_LBM_PHY (3 << 6) // PHY or external SerDesc loopback
+#define RTCL_RDMTS_HALF (0 << 8) // Free Buffer Threshold is 1/2 of RDLEN
+#define RTCL_RDMTS_QUARTER (1 << 8) // Free Buffer Threshold is 1/4 of RDLEN
+#define RTCL_RDMTS_EIGHTH (2 << 8) // Free Buffer Threshold is 1/8 of RDLEN
+#define RCTL_MO_36 (0 << 12) // Multicast Offset - bits 47:36
+#define RCTL_MO_35 (1 << 12) // Multicast Offset - bits 46:35
+#define RCTL_MO_34 (2 << 12) // Multicast Offset - bits 45:34
+#define RCTL_MO_32 (3 << 12) // Multicast Offset - bits 43:32
+#define RCTL_BAM (1 << 15) // Broadcast Accept Mode
+#define RCTL_VFE (1 << 18) // VLAN Filter Enable
+#define RCTL_CFIEN (1 << 19) // Canonical Form Indicator Enable
+#define RCTL_CFI (1 << 20) // Canonical Form Indicator Bit Value
+#define RCTL_DPF (1 << 22) // Discard Pause Frames
+#define RCTL_PMCF (1 << 23) // Pass MAC Control Frames
+#define RCTL_SECRC (1 << 26) // Strip Ethernet CRC
// Buffer Sizes
-#define RCTL_BSIZE_256 (3 << 16)
-#define RCTL_BSIZE_512 (2 << 16)
-#define RCTL_BSIZE_1024 (1 << 16)
-#define RCTL_BSIZE_2048 (0 << 16)
-#define RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
-#define RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
-#define RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
+#define RCTL_BSIZE_256 (3 << 16)
+#define RCTL_BSIZE_512 (2 << 16)
+#define RCTL_BSIZE_1024 (1 << 16)
+#define RCTL_BSIZE_2048 (0 << 16)
+#define RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
+#define RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
+#define RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
// Transmit Command
-#define CMD_EOP (1 << 0) // End of Packet
-#define CMD_IFCS (1 << 1) // Insert FCS
-#define CMD_IC (1 << 2) // Insert Checksum
-#define CMD_RS (1 << 3) // Report Status
-#define CMD_RPS (1 << 4) // Report Packet Sent
-#define CMD_VLE (1 << 6) // VLAN Packet Enable
-#define CMD_IDE (1 << 7) // Interrupt Delay Enable
+#define CMD_EOP (1 << 0) // End of Packet
+#define CMD_IFCS (1 << 1) // Insert FCS
+#define CMD_IC (1 << 2) // Insert Checksum
+#define CMD_RS (1 << 3) // Report Status
+#define CMD_RPS (1 << 4) // Report Packet Sent
+#define CMD_VLE (1 << 6) // VLAN Packet Enable
+#define CMD_IDE (1 << 7) // Interrupt Delay Enable
// TCTL Register
-#define TCTL_EN (1 << 1) // Transmit Enable
-#define TCTL_PSP (1 << 3) // Pad Short Packets
-#define TCTL_CT_SHIFT 4 // Collision Threshold
-#define TCTL_COLD_SHIFT 12 // Collision Distance
-#define TCTL_SWXOFF (1 << 22) // Software XOFF Transmission
-#define TCTL_RTLC (1 << 24) // Re-transmit on Late Collision
+#define TCTL_EN (1 << 1) // Transmit Enable
+#define TCTL_PSP (1 << 3) // Pad Short Packets
+#define TCTL_CT_SHIFT 4 // Collision Threshold
+#define TCTL_COLD_SHIFT 12 // Collision Distance
+#define TCTL_SWXOFF (1 << 22) // Software XOFF Transmission
+#define TCTL_RTLC (1 << 24) // Re-transmit on Late Collision
-#define TSTA_DD (1 << 0) // Descriptor Done
-#define TSTA_EC (1 << 1) // Excess Collisions
-#define TSTA_LC (1 << 2) // Late Collision
-#define LSTA_TU (1 << 3) // Transmit Underrun
+#define TSTA_DD (1 << 0) // Descriptor Done
+#define TSTA_EC (1 << 1) // Excess Collisions
+#define TSTA_LC (1 << 2) // Late Collision
+#define LSTA_TU (1 << 3) // Transmit Underrun
OwnPtr<E1000NetworkAdapter> E1000NetworkAdapter::autodetect()
{
static const PCI::ID qemu_bochs_vbox_id = { 0x8086, 0x100e };
PCI::Address found_address;
- PCI::enumerate_all([&] (const PCI::Address& address, PCI::ID id) {
+ PCI::enumerate_all([&](const PCI::Address& address, PCI::ID id) {
if (id == qemu_bochs_vbox_id) {
found_address = address;
return;
@@ -231,7 +231,7 @@ void E1000NetworkAdapter::initialize_rx_descriptors()
out32(REG_RXDESCHEAD, 0);
out32(REG_RXDESCTAIL, number_of_rx_descriptors - 1);
- out32(REG_RCTRL, RCTL_EN| RCTL_SBP| RCTL_UPE | RCTL_MPE | RCTL_LBM_NONE | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_8192);
+ out32(REG_RCTRL, RCTL_EN | RCTL_SBP | RCTL_UPE | RCTL_MPE | RCTL_LBM_NONE | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_8192);
}
void E1000NetworkAdapter::initialize_tx_descriptors()