Kernel: Add x2APIC support

This allows addressing all cores on more modern processors. For now,
we still have a hardcoded limit of 64 due to s_processors being a
static array.

1 files changed, 13 insertions, 13 deletions

diff --git a/Kernel/Interrupts/APIC.h b/Kernel/Interrupts/APIC.h
index e59ef33564..60f56333c0 100644
--- a/Kernel/Interrupts/APIC.h
+++ b/Kernel/Interrupts/APIC.h
@@ -47,11 +47,7 @@ public:
     u32 get_timer_divisor();
 
 private:
-    class ICRReg {
-        u32 m_low { 0 };
-        u32 m_high { 0 };
-
-    public:
+    struct ICRReg {
         enum DeliveryMode {
             Fixed = 0x0,
             LowPriority = 0x1,
@@ -79,14 +75,17 @@ private:
             AllExcludingSelf = 0x3,
         };
 
-        ICRReg(u8 vector, DeliveryMode delivery_mode, DestinationMode destination_mode, Level level, TriggerMode trigger_mode, DestinationShorthand destinationShort, u8 destination = 0)
-            : m_low(vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destinationShort << 18))
-            , m_high((u32)destination << 24)
-        {
-        }
+        u8 vector { 0 };
+        u32 destination { 0 };
+        DeliveryMode delivery_mode { DeliveryMode::Fixed };
+        DestinationMode destination_mode { DestinationMode::Physical };
+        Level level { Level::DeAssert };
+        TriggerMode trigger_mode { TriggerMode::Edge };
+        DestinationShorthand destination_short { DestinationShorthand::NoShorthand };
 
-        u32 low() const { return m_low; }
-        u32 high() const { return m_high; }
+        u32 x_low() const { return (u32)vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destination_short << 18); }
+        u32 x_high() const { return destination << 24; }
+        u64 x2_value() const { return ((u64)destination << 32) | x_low(); }
     };
 
     OwnPtr<Memory::Region> m_apic_base;
@@ -97,9 +96,10 @@ private:
     u32 m_processor_cnt { 0 };
     u32 m_processor_enabled_cnt { 0 };
     APICTimer* m_apic_timer { nullptr };
+    bool m_is_x2 { false };
 
     static PhysicalAddress get_base();
-    static void set_base(const PhysicalAddress& base);
+    void set_base(const PhysicalAddress& base);
     void write_register(u32 offset, u32 value);
     u32 read_register(u32 offset);
     void set_lvt(u32 offset, u8 interrupt);