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| author | Timon Kruiper <timonkruiper@gmail.com> | 2023-01-30 10:28:17 +0100 |
|---|---|---|
| committer | Linus Groh <mail@linusgroh.de> | 2023-02-08 18:19:48 +0000 |
| commit | 7be7324287b5a35e639acf5b2be9c5e9d3228981 (patch) | |
| tree | 9cdfcaf7573da25bf165ba3788c521c39e863f8d /Kernel/Arch | |
| parent | ecf45e191e47ab74750cbf98b026863d691650f6 (diff) | |
| download | serenity-7be7324287b5a35e639acf5b2be9c5e9d3228981.zip | |
Kernel/aarch64: Set correct ExecutionMode of PageFault
Adds a helper to aarch64/Registers.h to factor out the exception class
encoding.
Diffstat (limited to 'Kernel/Arch')
| -rw-r--r-- | Kernel/Arch/aarch64/Interrupts.cpp | 3 | ||||
| -rw-r--r-- | Kernel/Arch/aarch64/Registers.h | 5 |
2 files changed, 6 insertions, 2 deletions
diff --git a/Kernel/Arch/aarch64/Interrupts.cpp b/Kernel/Arch/aarch64/Interrupts.cpp index 3cddb3ee9c..d4301504f5 100644 --- a/Kernel/Arch/aarch64/Interrupts.cpp +++ b/Kernel/Arch/aarch64/Interrupts.cpp @@ -70,8 +70,7 @@ static PageFault page_fault_from_exception_syndrome_register(VirtualAddress faul fault.set_access((esr_el1.ISS & (1 << 6)) == (1 << 6) ? PageFault::Access::Write : PageFault::Access::Read); - // FIXME: Set correct mode - fault.set_mode(ExecutionMode::Kernel); + fault.set_mode(Aarch64::exception_class_is_data_or_instruction_abort_from_lower_exception_level(esr_el1.EC) ? ExecutionMode::User : ExecutionMode::Kernel); if (Aarch64::exception_class_is_instruction_abort(esr_el1.EC)) fault.set_instruction_fetch(true); diff --git a/Kernel/Arch/aarch64/Registers.h b/Kernel/Arch/aarch64/Registers.h index 5eac1c93e7..d3e8c11b4f 100644 --- a/Kernel/Arch/aarch64/Registers.h +++ b/Kernel/Arch/aarch64/Registers.h @@ -1167,6 +1167,11 @@ static inline bool exception_class_is_instruction_abort(u8 exception_class) return exception_class == 0x20 || exception_class == 0x21; } +static inline bool exception_class_is_data_or_instruction_abort_from_lower_exception_level(u8 exception_class) +{ + return exception_class == 0x20 || exception_class == 0x24; +} + // D17.2.37 ESR_EL1, Exception Syndrome Register (EL1) // ISS encoding for an exception from a Data Abort // DFSC, bits [5:0] |