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| author | Andrew Kaster <akaster@serenityos.org> | 2023-05-15 01:42:26 -0600 |
|---|---|---|
| committer | Andrew Kaster <andrewdkaster@gmail.com> | 2023-05-19 20:12:25 -0600 |
| commit | 28d2e266788e88ae595b4645ac03f9a04351b877 (patch) | |
| tree | 3b86107a0553ab3b79948097fdcc9fe69394bc04 /Kernel/Arch | |
| parent | f62c646c28e6b82509a026bb07f12eacc3e6c551 (diff) | |
| download | serenity-28d2e266788e88ae595b4645ac03f9a04351b877.zip | |
Kernel: Enable data and instruction cache on aarch64
Enabling these will fix the Unsupported Exclusive or Atomic access data
fault we get on bare metal Raspberry Pi 3. On A53/A57 chips (and newer),
atomic compare-exchange operations require the data cache to be enabled.
Diffstat (limited to 'Kernel/Arch')
| -rw-r--r-- | Kernel/Arch/aarch64/MMU.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/Kernel/Arch/aarch64/MMU.cpp b/Kernel/Arch/aarch64/MMU.cpp index c28c1e6f2c..65db387ddc 100644 --- a/Kernel/Arch/aarch64/MMU.cpp +++ b/Kernel/Arch/aarch64/MMU.cpp @@ -214,8 +214,10 @@ static void activate_mmu() Aarch64::TCR_EL1::write(tcr_el1); // Enable MMU in the system control register - Aarch64::SCTLR_EL1 sctlr_el1 = Aarch64::SCTLR_EL1::read(); + Aarch64::SCTLR_EL1 sctlr_el1 = Aarch64::SCTLR_EL1::reset_value(); sctlr_el1.M = 1; // Enable MMU + sctlr_el1.C = 1; // Enable data cache + sctlr_el1.I = 1; // Enable instruction cache Aarch64::SCTLR_EL1::write(sctlr_el1); Aarch64::Asm::flush(); |