Kernel/PCI: Hold a reference to DeviceIdentifier in the Device class

There are now 2 separate classes for almost the same object type:
- EnumerableDeviceIdentifier, which is used in the enumeration code for
  all PCI host controller classes. This is allowed to be moved and
  copied, as it doesn't support ref-counting.
- DeviceIdentifier, which inherits from EnumerableDeviceIdentifier. This
  class uses ref-counting, and is not allowed to be copied. It has a
  spinlock member in its structure to allow safely executing complicated
  IO sequences on a PCI device and its space configuration.
  There's a static method that allows a quick conversion from
  EnumerableDeviceIdentifier to DeviceIdentifier while creating a
  NonnullRefPtr out of it.

The reason for doing this is for the sake of integrity and reliablity of
the system in 2 places:
- Ensure that "complicated" tasks that rely on manipulating PCI device
  registers are done in a safe manner. For example, determining a PCI
  BAR space size requires multiple read and writes to the same register,
  and if another CPU tries to do something else with our selected
  register, then the result will be a catastrophe.
- Allow the PCI API to have a united form around a shared object which
  actually holds much more data than the PCI::Address structure. This is
  fundamental if we want to do certain types of optimizations, and be
  able to support more features of the PCI bus in the foreseeable
  future.

This patch already has several implications:
- All PCI::Device(s) hold a reference to a DeviceIdentifier structure
  being given originally from the PCI::Access singleton. This means that
  all instances of DeviceIdentifier structures are located in one place,
  and all references are pointing to that location. This ensures that
  locking the operation spinlock will take effect in all the appropriate
  places.
- We no longer support adding PCI host controllers and then immediately
  allow for enumerating it with a lambda function. It was found that
  this method is extremely broken and too much complicated to work
  reliably with the new paradigm being introduced in this patch. This
  means that for Volume Management Devices (Intel VMD devices), we
  simply first enumerate the PCI bus for such devices in the storage
  code, and if we find a device, we attach it in the PCI::Access method
  which will scan for devices behind that bridge and will add new
  DeviceIdentifier(s) objects to its internal Vector. Afterwards, we
  just continue as usual with scanning for actual storage controllers,
  so we will find a corresponding NVMe controllers if there were any
  behind that VMD bridge.

1 files changed, 13 insertions, 13 deletions

diff --git a/Kernel/Arch/x86_64/PCI/IDELegacyModeController.cpp b/Kernel/Arch/x86_64/PCI/IDELegacyModeController.cpp
index f5260ea1dc..080ac29518 100644
--- a/Kernel/Arch/x86_64/PCI/IDELegacyModeController.cpp
+++ b/Kernel/Arch/x86_64/PCI/IDELegacyModeController.cpp
@@ -18,9 +18,9 @@ namespace Kernel {
 UNMAP_AFTER_INIT ErrorOr<NonnullLockRefPtr<PCIIDELegacyModeController>> PCIIDELegacyModeController::initialize(PCI::DeviceIdentifier const& device_identifier, bool force_pio)
 {
     auto controller = TRY(adopt_nonnull_lock_ref_or_enomem(new (nothrow) PCIIDELegacyModeController(device_identifier)));
-    PCI::enable_io_space(device_identifier.address());
-    PCI::enable_memory_space(device_identifier.address());
-    PCI::enable_bus_mastering(device_identifier.address());
+    PCI::enable_io_space(device_identifier);
+    PCI::enable_memory_space(device_identifier);
+    PCI::enable_bus_mastering(device_identifier);
     ArmedScopeGuard disable_interrupts_on_failure([&] {
         controller->disable_pin_based_interrupts();
     });
@@ -31,7 +31,7 @@ UNMAP_AFTER_INIT ErrorOr<NonnullLockRefPtr<PCIIDELegacyModeController>> PCIIDELe
 }
 
 UNMAP_AFTER_INIT PCIIDELegacyModeController::PCIIDELegacyModeController(PCI::DeviceIdentifier const& device_identifier)
-    : PCI::Device(device_identifier.address())
+    : PCI::Device(const_cast<PCI::DeviceIdentifier&>(device_identifier))
     , m_prog_if(device_identifier.prog_if())
     , m_interrupt_line(device_identifier.interrupt_line())
 {
@@ -84,11 +84,11 @@ static char const* detect_controller_type(u8 programming_value)
 
 UNMAP_AFTER_INIT ErrorOr<void> PCIIDELegacyModeController::initialize_and_enumerate_channels(bool force_pio)
 {
-    dbgln("IDE controller @ {}: interrupt line was set to {}", pci_address(), m_interrupt_line.value());
-    dbgln("IDE controller @ {}: {}", pci_address(), detect_controller_type(m_prog_if.value()));
+    dbgln("IDE controller @ {}: interrupt line was set to {}", device_identifier().address(), m_interrupt_line.value());
+    dbgln("IDE controller @ {}: {}", device_identifier().address(), detect_controller_type(m_prog_if.value()));
     {
-        auto bus_master_base = IOAddress(PCI::get_BAR4(pci_address()) & (~1));
-        dbgln("IDE controller @ {}: bus master base was set to {}", pci_address(), bus_master_base);
+        auto bus_master_base = IOAddress(PCI::get_BAR4(device_identifier()) & (~1));
+        dbgln("IDE controller @ {}: bus master base was set to {}", device_identifier().address(), bus_master_base);
     }
 
     auto initialize_and_enumerate = [&force_pio](IDEChannel& channel) -> ErrorOr<void> {
@@ -106,8 +106,8 @@ UNMAP_AFTER_INIT ErrorOr<void> PCIIDELegacyModeController::initialize_and_enumer
         primary_base_io_window = TRY(IOWindow::create_for_io_space(IOAddress(0x1F0), 8));
         primary_control_io_window = TRY(IOWindow::create_for_io_space(IOAddress(0x3F6), 4));
     } else {
-        auto primary_base_io_window = TRY(IOWindow::create_for_pci_device_bar(pci_address(), PCI::HeaderType0BaseRegister::BAR0));
-        auto pci_primary_control_io_window = TRY(IOWindow::create_for_pci_device_bar(pci_address(), PCI::HeaderType0BaseRegister::BAR1));
+        auto primary_base_io_window = TRY(IOWindow::create_for_pci_device_bar(device_identifier(), PCI::HeaderType0BaseRegister::BAR0));
+        auto pci_primary_control_io_window = TRY(IOWindow::create_for_pci_device_bar(device_identifier(), PCI::HeaderType0BaseRegister::BAR1));
         // Note: the PCI IDE specification says we should access the IO address with an offset of 2
         // on native PCI IDE controllers.
         primary_control_io_window = TRY(pci_primary_control_io_window->create_from_io_window_with_offset(2, 4));
@@ -123,8 +123,8 @@ UNMAP_AFTER_INIT ErrorOr<void> PCIIDELegacyModeController::initialize_and_enumer
         secondary_base_io_window = TRY(IOWindow::create_for_io_space(IOAddress(0x170), 8));
         secondary_control_io_window = TRY(IOWindow::create_for_io_space(IOAddress(0x376), 4));
     } else {
-        secondary_base_io_window = TRY(IOWindow::create_for_pci_device_bar(pci_address(), PCI::HeaderType0BaseRegister::BAR2));
-        auto pci_secondary_control_io_window = TRY(IOWindow::create_for_pci_device_bar(pci_address(), PCI::HeaderType0BaseRegister::BAR3));
+        secondary_base_io_window = TRY(IOWindow::create_for_pci_device_bar(device_identifier(), PCI::HeaderType0BaseRegister::BAR2));
+        auto pci_secondary_control_io_window = TRY(IOWindow::create_for_pci_device_bar(device_identifier(), PCI::HeaderType0BaseRegister::BAR3));
         // Note: the PCI IDE specification says we should access the IO address with an offset of 2
         // on native PCI IDE controllers.
         secondary_control_io_window = TRY(pci_secondary_control_io_window->create_from_io_window_with_offset(2, 4));
@@ -132,7 +132,7 @@ UNMAP_AFTER_INIT ErrorOr<void> PCIIDELegacyModeController::initialize_and_enumer
     VERIFY(secondary_base_io_window);
     VERIFY(secondary_control_io_window);
 
-    auto primary_bus_master_io = TRY(IOWindow::create_for_pci_device_bar(pci_address(), PCI::HeaderType0BaseRegister::BAR4, 16));
+    auto primary_bus_master_io = TRY(IOWindow::create_for_pci_device_bar(device_identifier(), PCI::HeaderType0BaseRegister::BAR4, 16));
     auto secondary_bus_master_io = TRY(primary_bus_master_io->create_from_io_window_with_offset(8));
 
     // FIXME: On IOAPIC based system, this value might be completely wrong