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authorGunnar Beutner <gbeutner@serenityos.org>2021-07-01 23:02:21 +0200
committerAndreas Kling <kling@serenityos.org>2021-07-01 23:36:17 +0200
commitdb334b50d0a14c983e3218464ecf52f42e41b3de (patch)
tree102896a30c06d01d5638e8f5b29a64c5d814ef06 /Kernel/Arch/x86/x86_64
parent59ba316ac6e6315c3142e95916f977e8fe8655a7 (diff)
downloadserenity-db334b50d0a14c983e3218464ecf52f42e41b3de.zip
Kernel: Don't byteswap the ISR number on interrupt entry
Let's just add the padding before we jump to interrupt_common_asm_entry.
Diffstat (limited to 'Kernel/Arch/x86/x86_64')
-rw-r--r--Kernel/Arch/x86/x86_64/InterruptEntry.cpp7
1 files changed, 0 insertions, 7 deletions
diff --git a/Kernel/Arch/x86/x86_64/InterruptEntry.cpp b/Kernel/Arch/x86/x86_64/InterruptEntry.cpp
index 4426edbb24..cc1811106c 100644
--- a/Kernel/Arch/x86/x86_64/InterruptEntry.cpp
+++ b/Kernel/Arch/x86/x86_64/InterruptEntry.cpp
@@ -12,13 +12,6 @@
asm(
".globl interrupt_common_asm_entry\n"
"interrupt_common_asm_entry: \n"
- // add the padding field in RegisterState
- " subq $4, %rsp\n"
- " pushq %rax\n"
- " movl 12(%rsp), %eax\n"
- " movl $0, 12(%rsp)\n"
- " movl %eax, 8(%rsp)\n"
- " popq %rax\n"
// save all the other registers
" pushq %r15\n"
" pushq %r14\n"