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| author | Andreas Kling <awesomekling@gmail.com> | 2019-12-24 22:45:27 +0100 |
|---|---|---|
| committer | Andreas Kling <awesomekling@gmail.com> | 2019-12-24 22:45:27 +0100 |
| commit | 3623e359782d65aa5b460c15a8bfe1dbb0bc057f (patch) | |
| tree | 83ff9cf384ccc1c1ecb8a4affacbe23db2d677c2 | |
| parent | caa5191f74e06fe77eaca244de3a58ce3a015d56 (diff) | |
| download | serenity-3623e359782d65aa5b460c15a8bfe1dbb0bc057f.zip | |
Kernel: Oops, actually enable CR4.PGE (page table global bit)
Turns out we were setting the wrong bit here. Now we will actually keep
kernel memory mappings in the TLB across context switches.
| -rw-r--r-- | Kernel/VM/MemoryManager.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Kernel/VM/MemoryManager.cpp b/Kernel/VM/MemoryManager.cpp index d69eb86f66..0ebe60bfea 100644 --- a/Kernel/VM/MemoryManager.cpp +++ b/Kernel/VM/MemoryManager.cpp @@ -168,7 +168,7 @@ void MemoryManager::initialize_paging() // Turn on CR4.PGE so the CPU will respect the G bit in page tables. asm volatile( "mov %cr4, %eax\n" - "orl $0x10, %eax\n" + "orl $0x40, %eax\n" "mov %eax, %cr4\n"); asm volatile("movl %%eax, %%cr3" ::"a"(kernel_page_directory().cr3())); |