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author | Andreas Kling <awesomekling@gmail.com> | 2019-12-25 02:56:18 +0100 |
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committer | Andreas Kling <awesomekling@gmail.com> | 2019-12-25 02:58:03 +0100 |
commit | c9a5253ac28a22ff92f59f5a55adabe99b93e5de (patch) | |
tree | ed46fad4e542bdd19a6f40a1efe94871002d60ea | |
parent | 0e45b9423b059196e89ba369d4cd80e695775c2e (diff) | |
download | serenity-c9a5253ac28a22ff92f59f5a55adabe99b93e5de.zip |
Kernel: Uh, actually *actually* turn on CR4.PGE
I'm not sure how I managed to misread the location of this bit twice.
But I did! Here is finally the correct value, according to Intel:
"Page Global Enable (bit 7 of CR4)"
Jeez! :^)
-rw-r--r-- | Kernel/VM/MemoryManager.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Kernel/VM/MemoryManager.cpp b/Kernel/VM/MemoryManager.cpp index 0ebe60bfea..e7fd16ef46 100644 --- a/Kernel/VM/MemoryManager.cpp +++ b/Kernel/VM/MemoryManager.cpp @@ -168,7 +168,7 @@ void MemoryManager::initialize_paging() // Turn on CR4.PGE so the CPU will respect the G bit in page tables. asm volatile( "mov %cr4, %eax\n" - "orl $0x40, %eax\n" + "orl $0x80, %eax\n" "mov %eax, %cr4\n"); asm volatile("movl %%eax, %%cr3" ::"a"(kernel_page_directory().cr3())); |