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author | Gal Horowitz <galush.horowitz@gmail.com> | 2021-01-08 13:03:24 +0200 |
---|---|---|
committer | Andreas Kling <kling@serenityos.org> | 2021-01-08 12:17:06 +0100 |
commit | 2fd2396d6383fd8637b1159724264ae19936882a (patch) | |
tree | bdc58b301623bda24cc18eb98a1216884469a88b | |
parent | edc18ab4e60dcb412a23715ab6ae1a06a74e2fa4 (diff) | |
download | serenity-2fd2396d6383fd8637b1159724264ae19936882a.zip |
UserspaceEmulator: Fix incorrect shadowing on mov sign extend
Unlike zero-extend moves, the upper bytes are not just zeroed,
but rather are based on the sign bit of the source, which means
if the source is tainted, so should the upper bytes be.
-rw-r--r-- | DevTools/UserspaceEmulator/SoftCPU.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/DevTools/UserspaceEmulator/SoftCPU.cpp b/DevTools/UserspaceEmulator/SoftCPU.cpp index 15aaa9eb4a..07de4719b4 100644 --- a/DevTools/UserspaceEmulator/SoftCPU.cpp +++ b/DevTools/UserspaceEmulator/SoftCPU.cpp @@ -2449,19 +2449,19 @@ void SoftCPU::MOVSW(const X86::Instruction& insn) void SoftCPU::MOVSX_reg16_RM8(const X86::Instruction& insn) { auto src = insn.modrm().read8(*this, insn); - gpr16(insn.reg16()) = ValueWithShadow<u16>(sign_extended_to<u16>(src.value()), 0x0100 | (src.shadow())); + gpr16(insn.reg16()) = shadow_wrap_with_taint_from<u16>(sign_extended_to<u16>(src.value()), src.shadow()); } void SoftCPU::MOVSX_reg32_RM16(const X86::Instruction& insn) { auto src = insn.modrm().read16(*this, insn); - gpr32(insn.reg32()) = ValueWithShadow<u32>(sign_extended_to<u32>(src.value()), 0x01010000 | (src.shadow())); + gpr32(insn.reg32()) = shadow_wrap_with_taint_from<u32>(sign_extended_to<u32>(src.value()), src.shadow()); } void SoftCPU::MOVSX_reg32_RM8(const X86::Instruction& insn) { auto src = insn.modrm().read8(*this, insn); - gpr32(insn.reg32()) = ValueWithShadow<u32>(sign_extended_to<u32>(src.value()), 0x01010100 | (src.shadow())); + gpr32(insn.reg32()) = shadow_wrap_with_taint_from<u32>(sign_extended_to<u32>(src.value()), src.shadow()); } void SoftCPU::MOVZX_reg16_RM8(const X86::Instruction& insn) |