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authorLiav A <liavalb@gmail.com>2021-04-02 14:08:14 +0300
committerAndreas Kling <kling@serenityos.org>2021-04-03 11:57:23 +0200
commit27bf91ab87b675861a629dbedfddab0fa58a0c4f (patch)
tree57b1691d7c8a2b6d184a834d0e6b7628a14c70ff
parent2718d7c74cc7a3c5b125fe1ec89ab189547b1dd8 (diff)
downloadserenity-27bf91ab87b675861a629dbedfddab0fa58a0c4f.zip
Revert "Kernel/PCI: Allow to set the PCI IRQ line of a device"
This reverts commit 36a82188a88c95315e03f6fcede237bc66831702. This register is write-only for the firmware (BIOS), and read-only for us so we shouldn't set the PCI IRQ line never. The firmware figured out the IRQ routing to the PIC for us, so changing it won't affect anything. I was mistaken when I thought that changing the value of this register will allow us to change its interrupt line, like when changing a PCI BAR to relocate device resources as desired with the requirements of the OS.
-rw-r--r--Kernel/PCI/Access.cpp5
-rw-r--r--Kernel/PCI/Definitions.h1
2 files changed, 0 insertions, 6 deletions
diff --git a/Kernel/PCI/Access.cpp b/Kernel/PCI/Access.cpp
index de8b24a382..6197e6a7f1 100644
--- a/Kernel/PCI/Access.cpp
+++ b/Kernel/PCI/Access.cpp
@@ -222,11 +222,6 @@ u8 get_interrupt_line(Address address)
return read8(address, PCI_INTERRUPT_LINE);
}
-void set_interrupt_line(Address address, u8 new_line)
-{
- write8(address, PCI_INTERRUPT_LINE, new_line);
-}
-
u32 get_BAR0(Address address)
{
return read32(address, PCI_BAR0);
diff --git a/Kernel/PCI/Definitions.h b/Kernel/PCI/Definitions.h
index 968c548e84..23d3cf0da0 100644
--- a/Kernel/PCI/Definitions.h
+++ b/Kernel/PCI/Definitions.h
@@ -204,7 +204,6 @@ void enumerate(Function<void(Address, ID)> callback);
void enable_interrupt_line(Address);
void disable_interrupt_line(Address);
u8 get_interrupt_line(Address);
-void set_interrupt_line(Address, u8);
void raw_access(Address, u32, size_t, u32);
u32 get_BAR0(Address);
u32 get_BAR1(Address);