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/*
* QEMU AVR CPU
*
* Copyright (c) 2019-2020 Michael Rolnik
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/qemu-print.h"
#include "exec/exec-all.h"
#include "cpu.h"
#include "disas/dis-asm.h"
static void avr_cpu_set_pc(CPUState *cs, vaddr value)
{
AVRCPU *cpu = AVR_CPU(cs);
cpu->env.pc_w = value / 2; /* internally PC points to words */
}
static bool avr_cpu_has_work(CPUState *cs)
{
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = &cpu->env;
return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
&& cpu_interrupts_enabled(env);
}
static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = &cpu->env;
env->pc_w = tb->pc / 2; /* internally PC points to words */
}
static void avr_cpu_reset(DeviceState *ds)
{
CPUState *cs = CPU(ds);
AVRCPU *cpu = AVR_CPU(cs);
AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
CPUAVRState *env = &cpu->env;
mcc->parent_reset(ds);
env->pc_w = 0;
env->sregI = 1;
env->sregC = 0;
env->sregZ = 0;
env->sregN = 0;
env->sregV = 0;
env->sregS = 0;
env->sregH = 0;
env->sregT = 0;
env->rampD = 0;
env->rampX = 0;
env->rampY = 0;
env->rampZ = 0;
env->eind = 0;
env->sp = 0;
env->skip = 0;
memset(env->r, 0, sizeof(env->r));
tlb_flush(cs);
}
static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->mach = bfd_arch_avr;
info->print_insn = NULL;
}
static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
qemu_init_vcpu(cs);
cpu_reset(cs);
mcc->parent_realize(dev, errp);
}
static void avr_cpu_set_int(void *opaque, int irq, int level)
{
AVRCPU *cpu = opaque;
CPUAVRState *env = &cpu->env;
CPUState *cs = CPU(cpu);
uint64_t mask = (1ull << irq);
if (level) {
env->intsrc |= mask;
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
env->intsrc &= ~mask;
if (env->intsrc == 0) {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
}
static void avr_cpu_initfn(Object *obj)
{
AVRCPU *cpu = AVR_CPU(obj);
cpu_set_cpustate_pointers(cpu);
/* Set the number of interrupts supported by the CPU. */
qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
sizeof(cpu->env.intsrc) * 8);
}
static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
oc = object_class_by_name(cpu_model);
if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
object_class_is_abstract(oc)) {
oc = NULL;
}
return oc;
}
static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
{
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = &cpu->env;
int i;
qemu_fprintf(f, "\n");
qemu_fprintf(f, "PC: %06x\n", env->pc_w);
qemu_fprintf(f, "SP: %04x\n", env->sp);
qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16);
qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16);
qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16);
qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16);
qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16);
qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]);
qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]);
qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]);
qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n",
env->sregI ? 'I' : '-',
env->sregT ? 'T' : '-',
env->sregH ? 'H' : '-',
env->sregS ? 'S' : '-',
env->sregV ? 'V' : '-',
env->sregN ? '-' : 'N', /* Zf has negative logic */
env->sregZ ? 'Z' : '-',
env->sregC ? 'I' : '-');
qemu_fprintf(f, "SKIP: %02x\n", env->skip);
qemu_fprintf(f, "\n");
for (i = 0; i < ARRAY_SIZE(env->r); i++) {
qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]);
if ((i % 8) == 7) {
qemu_fprintf(f, "\n");
}
}
qemu_fprintf(f, "\n");
}
static void avr_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
mcc->parent_realize = dc->realize;
dc->realize = avr_cpu_realizefn;
device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset);
cc->class_by_name = avr_cpu_class_by_name;
cc->has_work = avr_cpu_has_work;
cc->do_interrupt = avr_cpu_do_interrupt;
cc->cpu_exec_interrupt = avr_cpu_exec_interrupt;
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
cc->tlb_fill = avr_cpu_tlb_fill;
cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->tcg_initialize = avr_cpu_tcg_init;
cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
cc->gdb_num_core_regs = 35;
cc->gdb_core_xml_file = "avr-cpu.xml";
}
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