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Unsolved issues/bugs in the mips/mipsel backend
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General
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- [ls][dw][lr] report broken (aligned) BadVAddr
- Missing per-CPU instruction decoding, currently all implemented
instructions are regarded as valid
- pcnet32 does not work for little endian emulation on big endian host
(probably not mips specific, but observable for mips-malta)
- CP1 enable/disable is checked at translation time, not at execution
time, so it will have delayed effect.
MIPS64
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- No 64bit TLB support
- no 64bit wide registers for FPU
- 64bit mul/div handling broken
"Generic" 4Kc system emulation
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- Doesn't correspond to any real hardware.
MALTA system emulation
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- We fake firmware support instead of doing the real thing
- Real firmware falls over when trying to init RAM, presumably due
to lacking I2C emulation.
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