1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
|
/*
* ARM helper routines
*
* Copyright (c) 2005 CodeSourcery, LLC
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "exec.h"
void raise_exception(int tt)
{
env->exception_index = tt;
cpu_loop_exit();
}
/* thread support */
spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
void cpu_lock(void)
{
spin_lock(&global_cpu_lock);
}
void cpu_unlock(void)
{
spin_unlock(&global_cpu_lock);
}
/* VFP support. */
void do_vfp_abss(void)
{
FT0s = float32_abs(FT0s);
}
void do_vfp_absd(void)
{
FT0d = float64_abs(FT0d);
}
void do_vfp_sqrts(void)
{
FT0s = float32_sqrt(FT0s, &env->vfp.fp_status);
}
void do_vfp_sqrtd(void)
{
FT0d = float64_sqrt(FT0d, &env->vfp.fp_status);
}
/* XXX: check quiet/signaling case */
#define DO_VFP_cmp(p, size) \
void do_vfp_cmp##p(void) \
{ \
uint32_t flags; \
switch(float ## size ## _compare_quiet(FT0##p, FT1##p, &env->vfp.fp_status)) {\
case 0: flags = 0x6; break;\
case -1: flags = 0x8; break;\
case 1: flags = 0x2; break;\
default: case 2: flags = 0x3; break;\
}\
env->vfp.fpscr = (flags << 28) | (env->vfp.fpscr & 0x0fffffff); \
FORCE_RET(); \
}\
\
void do_vfp_cmpe##p(void) \
{ \
uint32_t flags; \
switch(float ## size ## _compare(FT0##p, FT1##p, &env->vfp.fp_status)) {\
case 0: flags = 0x6; break;\
case -1: flags = 0x8; break;\
case 1: flags = 0x2; break;\
default: case 2: flags = 0x3; break;\
}\
env->vfp.fpscr = (flags << 28) | (env->vfp.fpscr & 0x0fffffff); \
FORCE_RET(); \
}
DO_VFP_cmp(s, 32)
DO_VFP_cmp(d, 64)
#undef DO_VFP_cmp
/* Convert host exception flags to vfp form. */
static inline int vfp_exceptbits_from_host(int host_bits)
{
int target_bits = 0;
if (host_bits & float_flag_invalid)
target_bits |= 1;
if (host_bits & float_flag_divbyzero)
target_bits |= 2;
if (host_bits & float_flag_overflow)
target_bits |= 4;
if (host_bits & float_flag_underflow)
target_bits |= 8;
if (host_bits & float_flag_inexact)
target_bits |= 0x10;
return target_bits;
}
/* Convert vfp exception flags to target form. */
static inline int vfp_exceptbits_to_host(int target_bits)
{
int host_bits = 0;
if (target_bits & 1)
host_bits |= float_flag_invalid;
if (target_bits & 2)
host_bits |= float_flag_divbyzero;
if (target_bits & 4)
host_bits |= float_flag_overflow;
if (target_bits & 8)
host_bits |= float_flag_underflow;
if (target_bits & 0x10)
host_bits |= float_flag_inexact;
return host_bits;
}
void do_vfp_set_fpscr(void)
{
int i;
uint32_t changed;
changed = env->vfp.fpscr;
env->vfp.fpscr = (T0 & 0xffc8ffff);
env->vfp.vec_len = (T0 >> 16) & 7;
env->vfp.vec_stride = (T0 >> 20) & 3;
changed ^= T0;
if (changed & (3 << 22)) {
i = (T0 >> 22) & 3;
switch (i) {
case 0:
i = float_round_nearest_even;
break;
case 1:
i = float_round_up;
break;
case 2:
i = float_round_down;
break;
case 3:
i = float_round_to_zero;
break;
}
set_float_rounding_mode(i, &env->vfp.fp_status);
}
i = vfp_exceptbits_to_host((T0 >> 8) & 0x1f);
set_float_exception_flags(i, &env->vfp.fp_status);
/* XXX: FZ and DN are not implemented. */
}
void do_vfp_get_fpscr(void)
{
int i;
T0 = (env->vfp.fpscr & 0xffc8ffff) | (env->vfp.vec_len << 16)
| (env->vfp.vec_stride << 20);
i = get_float_exception_flags(&env->vfp.fp_status);
T0 |= vfp_exceptbits_from_host(i);
}
#if !defined(CONFIG_USER_ONLY)
#define MMUSUFFIX _mmu
#define GETPC() (__builtin_return_address(0))
#define SHIFT 0
#include "softmmu_template.h"
#define SHIFT 1
#include "softmmu_template.h"
#define SHIFT 2
#include "softmmu_template.h"
#define SHIFT 3
#include "softmmu_template.h"
/* try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
{
TranslationBlock *tb;
CPUState *saved_env;
target_phys_addr_t pc;
int ret;
/* XXX: hack to restore env in all cases, even if not called from
generated code */
saved_env = env;
env = cpu_single_env;
ret = cpu_arm_handle_mmu_fault(env, addr, is_write, is_user, 1);
if (__builtin_expect(ret, 0)) {
if (retaddr) {
/* now we have a real cpu fault */
pc = (target_phys_addr_t)retaddr;
tb = tb_find_pc(pc);
if (tb) {
/* the PC is inside the translated code. It means that we have
a virtual CPU fault */
cpu_restore_state(tb, env, pc, NULL);
}
}
raise_exception(env->exception_index);
}
env = saved_env;
}
#endif
|