blob: c820d32ad5141979712ad2a8a822f0560c715f4e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
|
/*
* ARMv7M CPU object
*
* Copyright (c) 2017 Linaro Ltd
* Written by Peter Maydell <peter.maydell@linaro.org>
*
* This code is licensed under the GPL version 2 or later.
*/
#ifndef HW_ARM_ARMV7M_H
#define HW_ARM_ARMV7M_H
#include "hw/sysbus.h"
#include "hw/intc/armv7m_nvic.h"
#include "target/arm/idau.h"
#include "qom/object.h"
#define TYPE_BITBAND "ARM,bitband-memory"
typedef struct BitBandState BitBandState;
#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
struct BitBandState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
AddressSpace source_as;
MemoryRegion iomem;
uint32_t base;
MemoryRegion *source_memory;
};
#define TYPE_ARMV7M "armv7m"
typedef struct ARMv7MState ARMv7MState;
#define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M)
#define ARMV7M_NUM_BITBANDS 2
/* ARMv7M container object.
* + Unnamed GPIO input lines: external IRQ lines for the NVIC
* + Named GPIO output SYSRESETREQ: signalled for guest AIRCR.SYSRESETREQ.
* If this GPIO is not wired up then the NVIC will default to performing
* a qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET).
* + Property "cpu-type": CPU type to instantiate
* + Property "num-irq": number of external IRQ lines
* + Property "memory": MemoryRegion defining the physical address space
* that CPU accesses see. (The NVIC, bitbanding and other CPU-internal
* devices will be automatically layered on top of this view.)
* + Property "idau": IDAU interface (forwarded to CPU object)
* + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)
* + Property "vfp": enable VFP (forwarded to CPU object)
* + Property "dsp": enable DSP (forwarded to CPU object)
* + Property "enable-bitband": expose bitbanded IO
*/
struct ARMv7MState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
NVICState nvic;
BitBandState bitband[ARMV7M_NUM_BITBANDS];
ARMCPU *cpu;
/* MemoryRegion we pass to the CPU, with our devices layered on
* top of the ones the board provides in board_memory.
*/
MemoryRegion container;
/* Properties */
char *cpu_type;
/* MemoryRegion the board provides to us (with its devices, RAM, etc) */
MemoryRegion *board_memory;
Object *idau;
uint32_t init_svtor;
bool enable_bitband;
bool start_powered_off;
bool vfp;
bool dsp;
};
#endif
|
