blob: 75de3616ada1ec1e5c2e367d8faddc046975a802 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
|
#if !defined(__OPENPIC_H__)
#define __OPENPIC_H__
/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
enum {
OPENPIC_OUTPUT_INT = 0, /* IRQ */
OPENPIC_OUTPUT_CINT, /* critical IRQ */
OPENPIC_OUTPUT_MCK, /* Machine check event */
OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
OPENPIC_OUTPUT_RESET, /* Core reset event */
OPENPIC_OUTPUT_NB,
};
qemu_irq *openpic_init (PCIBus *bus, MemoryRegion **pmem, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out);
qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out);
#endif /* __OPENPIC_H__ */
|