1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
|
/*
* Exynos4210 I2C Bus Serial Interface Emulation
*
* Copyright (C) 2012 Samsung Electronics Co Ltd.
* Maksim Kozlov, <m.kozlov@samsung.com>
* Igor Mitsyanko, <i.mitsyanko@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*
*/
#include "qemu/osdep.h"
#include "qemu/timer.h"
#include "hw/sysbus.h"
#include "hw/i2c/i2c.h"
#ifndef EXYNOS4_I2C_DEBUG
#define EXYNOS4_I2C_DEBUG 0
#endif
#define TYPE_EXYNOS4_I2C "exynos4210.i2c"
#define EXYNOS4_I2C(obj) \
OBJECT_CHECK(Exynos4210I2CState, (obj), TYPE_EXYNOS4_I2C)
/* Exynos4210 I2C memory map */
#define EXYNOS4_I2C_MEM_SIZE 0x14
#define I2CCON_ADDR 0x00 /* control register */
#define I2CSTAT_ADDR 0x04 /* control/status register */
#define I2CADD_ADDR 0x08 /* address register */
#define I2CDS_ADDR 0x0c /* data shift register */
#define I2CLC_ADDR 0x10 /* line control register */
#define I2CCON_ACK_GEN (1 << 7)
#define I2CCON_INTRS_EN (1 << 5)
#define I2CCON_INT_PEND (1 << 4)
#define EXYNOS4_I2C_MODE(reg) (((reg) >> 6) & 3)
#define I2C_IN_MASTER_MODE(reg) (((reg) >> 6) & 2)
#define I2CMODE_MASTER_Rx 0x2
#define I2CMODE_MASTER_Tx 0x3
#define I2CSTAT_LAST_BIT (1 << 0)
#define I2CSTAT_OUTPUT_EN (1 << 4)
#define I2CSTAT_START_BUSY (1 << 5)
#if EXYNOS4_I2C_DEBUG
#define DPRINT(fmt, args...) \
do { fprintf(stderr, "QEMU I2C: "fmt, ## args); } while (0)
static const char *exynos4_i2c_get_regname(unsigned offset)
{
switch (offset) {
case I2CCON_ADDR:
return "I2CCON";
case I2CSTAT_ADDR:
return "I2CSTAT";
case I2CADD_ADDR:
return "I2CADD";
case I2CDS_ADDR:
return "I2CDS";
case I2CLC_ADDR:
return "I2CLC";
default:
return "[?]";
}
}
#else
#define DPRINT(fmt, args...) do { } while (0)
#endif
typedef struct Exynos4210I2CState {
SysBusDevice parent_obj;
MemoryRegion iomem;
I2CBus *bus;
qemu_irq irq;
uint8_t i2ccon;
uint8_t i2cstat;
uint8_t i2cadd;
uint8_t i2cds;
uint8_t i2clc;
bool scl_free;
} Exynos4210I2CState;
static inline void exynos4210_i2c_raise_interrupt(Exynos4210I2CState *s)
{
if (s->i2ccon & I2CCON_INTRS_EN) {
s->i2ccon |= I2CCON_INT_PEND;
qemu_irq_raise(s->irq);
}
}
static void exynos4210_i2c_data_receive(void *opaque)
{
Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
int ret;
s->i2cstat &= ~I2CSTAT_LAST_BIT;
s->scl_free = false;
ret = i2c_recv(s->bus);
if (ret < 0 && (s->i2ccon & I2CCON_ACK_GEN)) {
s->i2cstat |= I2CSTAT_LAST_BIT; /* Data is not acknowledged */
} else {
s->i2cds = ret;
}
exynos4210_i2c_raise_interrupt(s);
}
static void exynos4210_i2c_data_send(void *opaque)
{
Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
s->i2cstat &= ~I2CSTAT_LAST_BIT;
s->scl_free = false;
if (i2c_send(s->bus, s->i2cds) < 0 && (s->i2ccon & I2CCON_ACK_GEN)) {
s->i2cstat |= I2CSTAT_LAST_BIT;
}
exynos4210_i2c_raise_interrupt(s);
}
static uint64_t exynos4210_i2c_read(void *opaque, hwaddr offset,
unsigned size)
{
Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
uint8_t value;
switch (offset) {
case I2CCON_ADDR:
value = s->i2ccon;
break;
case I2CSTAT_ADDR:
value = s->i2cstat;
break;
case I2CADD_ADDR:
value = s->i2cadd;
break;
case I2CDS_ADDR:
value = s->i2cds;
s->scl_free = true;
if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Rx &&
(s->i2cstat & I2CSTAT_START_BUSY) &&
!(s->i2ccon & I2CCON_INT_PEND)) {
exynos4210_i2c_data_receive(s);
}
break;
case I2CLC_ADDR:
value = s->i2clc;
break;
default:
value = 0;
DPRINT("ERROR: Bad read offset 0x%x\n", (unsigned int)offset);
break;
}
DPRINT("read %s [0x%02x] -> 0x%02x\n", exynos4_i2c_get_regname(offset),
(unsigned int)offset, value);
return value;
}
static void exynos4210_i2c_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
uint8_t v = value & 0xff;
DPRINT("write %s [0x%02x] <- 0x%02x\n", exynos4_i2c_get_regname(offset),
(unsigned int)offset, v);
switch (offset) {
case I2CCON_ADDR:
s->i2ccon = (v & ~I2CCON_INT_PEND) | (s->i2ccon & I2CCON_INT_PEND);
if ((s->i2ccon & I2CCON_INT_PEND) && !(v & I2CCON_INT_PEND)) {
s->i2ccon &= ~I2CCON_INT_PEND;
qemu_irq_lower(s->irq);
if (!(s->i2ccon & I2CCON_INTRS_EN)) {
s->i2cstat &= ~I2CSTAT_START_BUSY;
}
if (s->i2cstat & I2CSTAT_START_BUSY) {
if (s->scl_free) {
if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Tx) {
exynos4210_i2c_data_send(s);
} else if (EXYNOS4_I2C_MODE(s->i2cstat) ==
I2CMODE_MASTER_Rx) {
exynos4210_i2c_data_receive(s);
}
} else {
s->i2ccon |= I2CCON_INT_PEND;
qemu_irq_raise(s->irq);
}
}
}
break;
case I2CSTAT_ADDR:
s->i2cstat =
(s->i2cstat & I2CSTAT_START_BUSY) | (v & ~I2CSTAT_START_BUSY);
if (!(s->i2cstat & I2CSTAT_OUTPUT_EN)) {
s->i2cstat &= ~I2CSTAT_START_BUSY;
s->scl_free = true;
qemu_irq_lower(s->irq);
break;
}
/* Nothing to do if in i2c slave mode */
if (!I2C_IN_MASTER_MODE(s->i2cstat)) {
break;
}
if (v & I2CSTAT_START_BUSY) {
s->i2cstat &= ~I2CSTAT_LAST_BIT;
s->i2cstat |= I2CSTAT_START_BUSY; /* Line is busy */
s->scl_free = false;
/* Generate start bit and send slave address */
if (i2c_start_transfer(s->bus, s->i2cds >> 1, s->i2cds & 0x1) &&
(s->i2ccon & I2CCON_ACK_GEN)) {
s->i2cstat |= I2CSTAT_LAST_BIT;
} else if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Rx) {
exynos4210_i2c_data_receive(s);
}
exynos4210_i2c_raise_interrupt(s);
} else {
i2c_end_transfer(s->bus);
if (!(s->i2ccon & I2CCON_INT_PEND)) {
s->i2cstat &= ~I2CSTAT_START_BUSY;
}
s->scl_free = true;
}
break;
case I2CADD_ADDR:
if ((s->i2cstat & I2CSTAT_OUTPUT_EN) == 0) {
s->i2cadd = v;
}
break;
case I2CDS_ADDR:
if (s->i2cstat & I2CSTAT_OUTPUT_EN) {
s->i2cds = v;
s->scl_free = true;
if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Tx &&
(s->i2cstat & I2CSTAT_START_BUSY) &&
!(s->i2ccon & I2CCON_INT_PEND)) {
exynos4210_i2c_data_send(s);
}
}
break;
case I2CLC_ADDR:
s->i2clc = v;
break;
default:
DPRINT("ERROR: Bad write offset 0x%x\n", (unsigned int)offset);
break;
}
}
static const MemoryRegionOps exynos4210_i2c_ops = {
.read = exynos4210_i2c_read,
.write = exynos4210_i2c_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription exynos4210_i2c_vmstate = {
.name = "exynos4210.i2c",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(i2ccon, Exynos4210I2CState),
VMSTATE_UINT8(i2cstat, Exynos4210I2CState),
VMSTATE_UINT8(i2cds, Exynos4210I2CState),
VMSTATE_UINT8(i2cadd, Exynos4210I2CState),
VMSTATE_UINT8(i2clc, Exynos4210I2CState),
VMSTATE_BOOL(scl_free, Exynos4210I2CState),
VMSTATE_END_OF_LIST()
}
};
static void exynos4210_i2c_reset(DeviceState *d)
{
Exynos4210I2CState *s = EXYNOS4_I2C(d);
s->i2ccon = 0x00;
s->i2cstat = 0x00;
s->i2cds = 0xFF;
s->i2clc = 0x00;
s->i2cadd = 0xFF;
s->scl_free = true;
}
static void exynos4210_i2c_init(Object *obj)
{
DeviceState *dev = DEVICE(obj);
Exynos4210I2CState *s = EXYNOS4_I2C(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, obj, &exynos4210_i2c_ops, s,
TYPE_EXYNOS4_I2C, EXYNOS4_I2C_MEM_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
s->bus = i2c_init_bus(dev, "i2c");
}
static void exynos4210_i2c_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &exynos4210_i2c_vmstate;
dc->reset = exynos4210_i2c_reset;
}
static const TypeInfo exynos4210_i2c_type_info = {
.name = TYPE_EXYNOS4_I2C,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Exynos4210I2CState),
.instance_init = exynos4210_i2c_init,
.class_init = exynos4210_i2c_class_init,
};
static void exynos4210_i2c_register_types(void)
{
type_register_static(&exynos4210_i2c_type_info);
}
type_init(exynos4210_i2c_register_types)
|