From e2a2b0b9187308c450a109ff967f720af4e399e6 Mon Sep 17 00:00:00 2001 From: Michael Rolnik Date: Thu, 6 Feb 2020 23:08:31 +0100 Subject: target/avr: CPU class: Add memory management support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch introduces three memory-management-related functions that will become part of AVR CPU class object. [AM: Split a larger AVR introduction patch into logical units] Suggested-by: Aleksandar Markovic Co-developed-by: Michael Rolnik Co-developed-by: Sarah Harris Signed-off-by: Michael Rolnik Signed-off-by: Sarah Harris Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Acked-by: Igor Mammedov Tested-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth Message-Id: <20200705140315.260514-5-huth@tuxfamily.org> Signed-off-by: Philippe Mathieu-Daudé --- target/avr/cpu.c | 3 +++ target/avr/helper.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) (limited to 'target/avr') diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 854e7ee1ff..6c68e6e4ab 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -203,6 +203,9 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->cpu_exec_interrupt = avr_cpu_exec_interrupt; cc->dump_state = avr_cpu_dump_state; cc->set_pc = avr_cpu_set_pc; + cc->memory_rw_debug = avr_cpu_memory_rw_debug; + cc->get_phys_page_debug = avr_cpu_get_phys_page_debug; + cc->tlb_fill = avr_cpu_tlb_fill; cc->disas_set_info = avr_cpu_disas_set_info; cc->tcg_initialize = avr_cpu_tcg_init; cc->synchronize_from_tb = avr_cpu_synchronize_from_tb; diff --git a/target/avr/helper.c b/target/avr/helper.c index 7174e4858e..d6985ff3f4 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -87,3 +87,53 @@ void avr_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; } + +int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf, + int len, bool is_write) +{ + return cpu_memory_rw_debug(cs, addr, buf, len, is_write); +} + +hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + return addr; /* I assume 1:1 address correspondance */ +} + +bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + int prot = 0; + MemTxAttrs attrs = {}; + uint32_t paddr; + + address &= TARGET_PAGE_MASK; + + if (mmu_idx == MMU_CODE_IDX) { + /* access to code in flash */ + paddr = OFFSET_CODE + address; + prot = PAGE_READ | PAGE_EXEC; + if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) { + error_report("execution left flash memory"); + abort(); + } + } else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) { + /* + * access to CPU registers, exit and rebuilt this TB to use full access + * incase it touches specially handled registers like SREG or SP + */ + AVRCPU *cpu = AVR_CPU(cs); + CPUAVRState *env = &cpu->env; + env->fullacc = 1; + cpu_loop_exit_restore(cs, retaddr); + } else { + /* access to memory. nothing special */ + paddr = OFFSET_DATA + address; + prot = PAGE_READ | PAGE_WRITE; + } + + tlb_set_page_with_attrs(cs, address, paddr, attrs, prot, + mmu_idx, TARGET_PAGE_SIZE); + + return true; +} -- cgit v1.2.3