From 65e4655c609a4a2fd428459d3efb62b704488fd6 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 21 Jan 2019 10:23:12 +0000 Subject: target/arm: Move cpu_mmu_index out of line This function is, or will shortly become, too big to inline. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190108223129.5570-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'target/arm/helper.c') diff --git a/target/arm/helper.c b/target/arm/helper.c index caea722c9b..25a7992941 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12949,6 +12949,50 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, + bool secstate, bool priv) +{ + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; + + if (priv) { + mmu_idx |= ARM_MMU_IDX_M_PRIV; + } + + if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; + } + + if (secstate) { + mmu_idx |= ARM_MMU_IDX_M_S; + } + + return mmu_idx; +} + +/* Return the MMU index for a v7M CPU in the specified security state */ +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + bool priv = arm_current_el(env) != 0; + + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); +} + +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + int el = arm_current_el(env); + + if (arm_feature(env, ARM_FEATURE_M)) { + ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); + + return arm_to_core_mmu_idx(mmu_idx); + } + + if (el < 2 && arm_is_secure_below_el3(env)) { + return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); + } + return el; +} + void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { -- cgit v1.2.3