From e60ec06357470db5a0f25901ca19b6237e6da927 Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Thu, 25 Jun 2015 00:24:14 +0100 Subject: target-mips: add microMIPS TLBINV, TLBINVF Add microMIPS TLBINV, TLBINVF Signed-off-by: Yongbok Kim Reviewed-by: Aurelien Jarno Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- target-mips/translate.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'target-mips') diff --git a/target-mips/translate.c b/target-mips/translate.c index 02c2523207..abff2ab564 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12243,6 +12243,8 @@ enum { TLBR = 0x1, TLBWI = 0x2, TLBWR = 0x3, + TLBINV = 0x4, + TLBINVF = 0x5, WAIT = 0x9, IRET = 0xd, DERET = 0xe, @@ -13027,6 +13029,12 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) case TLBWR: mips32_op = OPC_TLBWR; goto do_cp0; + case TLBINV: + mips32_op = OPC_TLBINV; + goto do_cp0; + case TLBINVF: + mips32_op = OPC_TLBINVF; + goto do_cp0; case WAIT: mips32_op = OPC_WAIT; goto do_cp0; -- cgit v1.2.3