From 01bc435b44b8802cc4697faa07d908684afbce4e Mon Sep 17 00:00:00 2001 From: Yongbok Kim Date: Wed, 3 Feb 2016 12:31:07 +0000 Subject: target-mips: implement R6 multi-threading MIPS Release 6 provides multi-threading features which replace pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new CP0.Config5.VP (Virtual Processor) bit which indicates presence of multi-threading support which includes CP0.GlobalNumber register and DVP/EVP instructions. Signed-off-by: Yongbok Kim Signed-off-by: Leon Alrae --- target-mips/helper.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'target-mips/helper.h') diff --git a/target-mips/helper.h b/target-mips/helper.h index 95b9149d89..1bc8bb20d1 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -176,6 +176,10 @@ DEF_HELPER_0(dmt, tl) DEF_HELPER_0(emt, tl) DEF_HELPER_1(dvpe, tl, env) DEF_HELPER_1(evpe, tl, env) + +/* R6 Multi-threading */ +DEF_HELPER_1(dvp, tl, env) +DEF_HELPER_1(evp, tl, env) #endif /* !CONFIG_USER_ONLY */ /* microMIPS functions */ -- cgit v1.2.3