From f0ec31b1e21718b728753bcbfad54862a587050f Mon Sep 17 00:00:00 2001 From: Suraj Jitindar Singh Date: Thu, 28 Nov 2019 14:46:57 +0100 Subject: target/ppc: Add SPR TBU40 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The spr TBU40 is used to set the upper 40 bits of the timebase register, present on POWER5+ and later processors. This register can only be written by the hypervisor, and cannot be read. Signed-off-by: Suraj Jitindar Singh Reviewed-by: David Gibson Signed-off-by: Cédric Le Goater Message-Id: <20191128134700.16091-5-clg@kaod.org> Signed-off-by: David Gibson --- hw/ppc/ppc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'hw/ppc') diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 2856d69495..4c5fa29399 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -698,6 +698,19 @@ void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value) &tb_env->vtb_offset, value); } +void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value) +{ + ppc_tb_t *tb_env = env->tb_env; + uint64_t tb; + + tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + tb_env->tb_offset); + tb &= 0xFFFFFFUL; + tb |= (value & ~0xFFFFFFUL); + cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + &tb_env->tb_offset, tb); +} + static void cpu_ppc_tb_stop (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; -- cgit v1.2.3