From 83d5e19d3eedcf533d8be009a03c167b7e1ccf2e Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Tue, 20 Oct 2020 12:59:38 +0200 Subject: hw/arm/highbank: Silence warnings about missing fallthrough statements When compiling with -Werror=implicit-fallthrough, gcc complains about missing fallthrough annotations in this file. Looking at the code, the fallthrough is very likely intended here, so add some comments to silence the compiler warnings. Signed-off-by: Thomas Huth Message-id: 20201020105938.23209-1-thuth@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/highbank.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index da0510d7ce..f71087860d 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -92,10 +92,12 @@ static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) address_space_stl_notdirty(&address_space_memory, SMP_BOOT_REG + 0x30, 0, MEMTXATTRS_UNSPECIFIED, NULL); + /* fallthrough */ case 3: address_space_stl_notdirty(&address_space_memory, SMP_BOOT_REG + 0x20, 0, MEMTXATTRS_UNSPECIFIED, NULL); + /* fallthrough */ case 2: address_space_stl_notdirty(&address_space_memory, SMP_BOOT_REG + 0x10, 0, -- cgit v1.2.3 From 7854104897444027759d805c133d9ea16c6a6c47 Mon Sep 17 00:00:00 2001 From: Pavel Dovgalyuk Date: Fri, 23 Oct 2020 10:35:49 +0300 Subject: hw/arm: fix min_cpus for xlnx-versal-virt platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch sets min_cpus field for xlnx-versal-virt platform, because it always creates XLNX_VERSAL_NR_ACPUS cpus even with -smp 1 command line option. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias Message-id: 160343854912.8460.17915238517799132371.stgit@pasha-ThinkPad-X280 Signed-off-by: Peter Maydell --- hw/arm/xlnx-versal-virt.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/arm') diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 03e23201b1..ee1282241e 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -561,6 +561,7 @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data) mc->desc = "Xilinx Versal Virtual development board"; mc->init = versal_virt_init; + mc->min_cpus = XLNX_VERSAL_NR_ACPUS; mc->max_cpus = XLNX_VERSAL_NR_ACPUS; mc->default_cpus = XLNX_VERSAL_NR_ACPUS; mc->no_cdrom = true; -- cgit v1.2.3 From 7d378ed6e3b4a26f4da887fcccc4c6f1db3dcd42 Mon Sep 17 00:00:00 2001 From: Hao Wu Date: Fri, 23 Oct 2020 14:06:34 -0700 Subject: hw/timer: Adding watchdog for NPCM7XX Timer. The watchdog is part of NPCM7XX's timer module. Its behavior is controlled by the WTCR register in the timer. When enabled, the watchdog issues an interrupt signal after a pre-set amount of cycles, and issues a reset signal shortly after that. Reviewed-by: Tyrone Ting Signed-off-by: Hao Wu Signed-off-by: Havard Skinnemoen Reviewed-by: Peter Maydell [PMM: deleted blank line at end of npcm_watchdog_timer-test.c] Signed-off-by: Peter Maydell --- hw/arm/npcm7xx.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 037f3a26f2..c341dcab8b 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -86,6 +86,9 @@ enum NPCM7xxInterrupt { NPCM7XX_TIMER12_IRQ, NPCM7XX_TIMER13_IRQ, NPCM7XX_TIMER14_IRQ, + NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */ + NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */ + NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ }; /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */ @@ -353,6 +356,15 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) qemu_irq irq = npcm7xx_irq(s, first_irq + j); sysbus_connect_irq(sbd, j, irq); } + + /* IRQ for watchdogs */ + sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL, + npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i)); + /* GPIO that connects clk module with watchdog */ + qdev_connect_gpio_out_named(DEVICE(&s->tim[i]), + NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0, + qdev_get_gpio_in_named(DEVICE(&s->clk), + NPCM7XX_WATCHDOG_RESET_GPIO_IN, i)); } /* UART0..3 (16550 compatible) */ -- cgit v1.2.3 From 326ccfe240ca9ef4f659a241b39390fa956e999b Mon Sep 17 00:00:00 2001 From: Havard Skinnemoen Date: Fri, 23 Oct 2020 14:06:35 -0700 Subject: hw/misc: Add npcm7xx random number generator The RNG module returns a byte of randomness when the Data Valid bit is set. This implementation ignores the prescaler setting, and loads a new value into RNGD every time RNGCS is read while the RNG is enabled and random data is available. A qtest featuring some simple randomness tests is included. Reviewed-by: Tyrone Ting Reviewed-by: Peter Maydell Signed-off-by: Havard Skinnemoen Signed-off-by: Peter Maydell --- hw/arm/npcm7xx.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'hw/arm') diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index c341dcab8b..cb4db41c54 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -44,6 +44,7 @@ #define NPCM7XX_GCR_BA (0xf0800000) #define NPCM7XX_CLK_BA (0xf0801000) #define NPCM7XX_MC_BA (0xf0824000) +#define NPCM7XX_RNG_BA (0xf000b000) /* Internal AHB SRAM */ #define NPCM7XX_RAM3_BA (0xc0008000) @@ -256,6 +257,7 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, "otp2", &s->fuse_array, TYPE_NPCM7XX_FUSE_ARRAY); object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); + object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); for (i = 0; i < ARRAY_SIZE(s->tim); i++) { object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); @@ -374,6 +376,10 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) serial_hd(i), DEVICE_LITTLE_ENDIAN); } + /* Random Number Generator. Cannot fail. */ + sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA); + /* * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects * specified, but this is a programming error. @@ -412,7 +418,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); - create_unimplemented_device("npcm7xx.rng", 0xf000b000, 4 * KiB); create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB); create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB); -- cgit v1.2.3 From e23e7b12594ec0804c2d9f509f71841c82a62d1c Mon Sep 17 00:00:00 2001 From: Havard Skinnemoen Date: Fri, 23 Oct 2020 14:06:36 -0700 Subject: hw/arm/npcm7xx: Add EHCI and OHCI controllers The NPCM730 and NPCM750 chips have a single USB host port shared between a USB 2.0 EHCI host controller and a USB 1.1 OHCI host controller. This adds support for both of them. Testing notes: * With -device usb-kbd, qemu will automatically insert a full-speed hub, and the keyboard becomes controlled by the OHCI controller. * With -device usb-kbd,bus=usb-bus.0,port=1, the keyboard is directly attached to the port without any hubs, and the device becomes controlled by the EHCI controller since it's high speed capable. * With -device usb-kbd,bus=usb-bus.0,port=1,usb_version=1, the keyboard is directly attached to the port, but it only advertises itself as full-speed capable, so it becomes controlled by the OHCI controller. In all cases, the keyboard device enumerates correctly. Reviewed-by: Tyrone Ting Reviewed-by: Gerd Hoffmann Signed-off-by: Havard Skinnemoen Signed-off-by: Peter Maydell --- hw/arm/npcm7xx.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) (limited to 'hw/arm') diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index cb4db41c54..c1d122576b 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -46,6 +46,10 @@ #define NPCM7XX_MC_BA (0xf0824000) #define NPCM7XX_RNG_BA (0xf000b000) +/* USB Host modules */ +#define NPCM7XX_EHCI_BA (0xf0806000) +#define NPCM7XX_OHCI_BA (0xf0807000) + /* Internal AHB SRAM */ #define NPCM7XX_RAM3_BA (0xc0008000) #define NPCM7XX_RAM3_SZ (4 * KiB) @@ -90,6 +94,8 @@ enum NPCM7xxInterrupt { NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */ NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */ NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ + NPCM7XX_EHCI_IRQ = 61, + NPCM7XX_OHCI_IRQ = 62, }; /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */ @@ -263,6 +269,9 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); } + object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI); + object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI); + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu)); for (i = 0; i < ARRAY_SIZE(s->fiu); i++) { object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i], @@ -380,6 +389,22 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA); + /* USB Host */ + object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true, + &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0, + npcm7xx_irq(s, NPCM7XX_EHCI_IRQ)); + + object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0", + &error_abort); + object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0, + npcm7xx_irq(s, NPCM7XX_OHCI_IRQ)); + /* * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects * specified, but this is a programming error. @@ -464,8 +489,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB); - create_unimplemented_device("npcm7xx.ehci", 0xf0806000, 4 * KiB); - create_unimplemented_device("npcm7xx.ohci", 0xf0807000, 4 * KiB); create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB); create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB); create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB); -- cgit v1.2.3 From 526dbbe087475599589ada4df70a337c09ae0f3f Mon Sep 17 00:00:00 2001 From: Havard Skinnemoen Date: Fri, 23 Oct 2020 14:06:37 -0700 Subject: hw/gpio: Add GPIO model for Nuvoton NPCM7xx The NPCM7xx chips have multiple GPIO controllers that are mostly identical except for some minor differences like the reset values of some registers. Each controller controls up to 32 pins. Each individual pin is modeled as a pair of unnamed GPIOs -- one for emitting the actual pin state, and one for driving the pin externally. Like the nRF51 GPIO controller, a gpio level may be negative, which means the pin is not driven, or floating. Reviewed-by: Tyrone Ting Signed-off-by: Havard Skinnemoen Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/npcm7xx.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index c1d122576b..47e2b6fc40 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -96,6 +96,14 @@ enum NPCM7xxInterrupt { NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ NPCM7XX_EHCI_IRQ = 61, NPCM7XX_OHCI_IRQ = 62, + NPCM7XX_GPIO0_IRQ = 116, + NPCM7XX_GPIO1_IRQ, + NPCM7XX_GPIO2_IRQ, + NPCM7XX_GPIO3_IRQ, + NPCM7XX_GPIO4_IRQ, + NPCM7XX_GPIO5_IRQ, + NPCM7XX_GPIO6_IRQ, + NPCM7XX_GPIO7_IRQ, }; /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */ @@ -130,6 +138,55 @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = { 0xb8000000, /* CS3 */ }; +static const struct { + hwaddr regs_addr; + uint32_t unconnected_pins; + uint32_t reset_pu; + uint32_t reset_pd; + uint32_t reset_osrc; + uint32_t reset_odsc; +} npcm7xx_gpio[] = { + { + .regs_addr = 0xf0010000, + .reset_pu = 0xff03ffff, + .reset_pd = 0x00fc0000, + }, { + .regs_addr = 0xf0011000, + .unconnected_pins = 0x0000001e, + .reset_pu = 0xfefffe07, + .reset_pd = 0x010001e0, + }, { + .regs_addr = 0xf0012000, + .reset_pu = 0x780fffff, + .reset_pd = 0x07f00000, + .reset_odsc = 0x00700000, + }, { + .regs_addr = 0xf0013000, + .reset_pu = 0x00fc0000, + .reset_pd = 0xff000000, + }, { + .regs_addr = 0xf0014000, + .reset_pu = 0xffffffff, + }, { + .regs_addr = 0xf0015000, + .reset_pu = 0xbf83f801, + .reset_pd = 0x007c0000, + .reset_osrc = 0x000000f1, + .reset_odsc = 0x3f9f80f1, + }, { + .regs_addr = 0xf0016000, + .reset_pu = 0xfc00f801, + .reset_pd = 0x000007fe, + .reset_odsc = 0x00000800, + }, { + .regs_addr = 0xf0017000, + .unconnected_pins = 0xffffff00, + .reset_pu = 0x0000007f, + .reset_osrc = 0x0000007f, + .reset_odsc = 0x0000007f, + }, +}; + static const struct { const char *name; hwaddr regs_addr; @@ -269,6 +326,10 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); } + for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { + object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO); + } + object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI); object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI); @@ -389,6 +450,25 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA); + /* GPIO modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio)); + for (i = 0; i < ARRAY_SIZE(s->gpio); i++) { + Object *obj = OBJECT(&s->gpio[i]); + + object_property_set_uint(obj, "reset-pullup", + npcm7xx_gpio[i].reset_pu, &error_abort); + object_property_set_uint(obj, "reset-pulldown", + npcm7xx_gpio[i].reset_pd, &error_abort); + object_property_set_uint(obj, "reset-osrc", + npcm7xx_gpio[i].reset_osrc, &error_abort); + object_property_set_uint(obj, "reset-odsc", + npcm7xx_gpio[i].reset_odsc, &error_abort); + sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr); + sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, + npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i)); + } + /* USB Host */ object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true, &error_abort); -- cgit v1.2.3 From a55aab618163f9ffd8b5cbf737d4e57875264510 Mon Sep 17 00:00:00 2001 From: Zenghui Yu Date: Mon, 19 Oct 2020 17:15:08 +0800 Subject: hw/arm/smmuv3: Set the restoration priority of the vSMMUv3 explicitly Ensure the vSMMUv3 will be restored before all PCIe devices so that DMA translation can work properly during migration. Signed-off-by: Zenghui Yu Message-id: 20201019091508.197-1-yuzenghui@huawei.com Acked-by: Eric Auger Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/arm') diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 0122700e72..2017ba7a5a 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1440,6 +1440,7 @@ static const VMStateDescription vmstate_smmuv3 = { .name = "smmuv3", .version_id = 1, .minimum_version_id = 1, + .priority = MIG_PRI_IOMMU, .fields = (VMStateField[]) { VMSTATE_UINT32(features, SMMUv3State), VMSTATE_UINT8(sid_size, SMMUv3State), -- cgit v1.2.3 From 58b350280e9782bf564bf55cf872edb8143a49a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 24 Oct 2020 19:01:19 +0200 Subject: hw/arm/bcm2836: Restrict BCM283XInfo declaration to C source MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No code out of bcm2836.c uses (or requires) the BCM283XInfo declarations. Move it locally to the C source file. Reviewed-by: Luc Michel Signed-off-by: Philippe Mathieu-Daudé Message-id: 20201024170127.3592182-2-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/bcm2836.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index f15cc3b405..e7cc2c930d 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -17,6 +17,15 @@ #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" +typedef struct BCM283XInfo BCM283XInfo; + +typedef struct BCM283XClass { + /*< private >*/ + DeviceClass parent_class; + /*< public >*/ + const BCM283XInfo *info; +} BCM283XClass; + struct BCM283XInfo { const char *name; const char *cpu_type; @@ -25,6 +34,11 @@ struct BCM283XInfo { int clusterid; }; +#define BCM283X_CLASS(klass) \ + OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) +#define BCM283X_GET_CLASS(obj) \ + OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) + static const BCM283XInfo bcm283x_socs[] = { { .name = TYPE_BCM2836, -- cgit v1.2.3 From 34d1a4f591efd22ed7ff9c883f1328eca6b0741f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 24 Oct 2020 19:01:20 +0200 Subject: hw/arm/bcm2836: QOM'ify more by adding class_init() to each SoC type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove usage of TypeInfo::class_data. Instead fill the fields in the corresponding class_init(). So far all children use the same values for almost all fields, but we are going to add the BCM2711/BCM2838 SoC for the raspi4 machine which use different fields. Reviewed-by: Igor Mammedov Signed-off-by: Philippe Mathieu-Daudé Message-id: 20201024170127.3592182-3-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/bcm2836.c | 110 ++++++++++++++++++++++++++----------------------------- 1 file changed, 52 insertions(+), 58 deletions(-) (limited to 'hw/arm') diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index e7cc2c930d..8f921d8e90 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -17,57 +17,31 @@ #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" -typedef struct BCM283XInfo BCM283XInfo; - typedef struct BCM283XClass { /*< private >*/ DeviceClass parent_class; /*< public >*/ - const BCM283XInfo *info; -} BCM283XClass; - -struct BCM283XInfo { const char *name; const char *cpu_type; hwaddr peri_base; /* Peripheral base address seen by the CPU */ hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ int clusterid; -}; +} BCM283XClass; #define BCM283X_CLASS(klass) \ OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) #define BCM283X_GET_CLASS(obj) \ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) -static const BCM283XInfo bcm283x_socs[] = { - { - .name = TYPE_BCM2836, - .cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"), - .peri_base = 0x3f000000, - .ctrl_base = 0x40000000, - .clusterid = 0xf, - }, -#ifdef TARGET_AARCH64 - { - .name = TYPE_BCM2837, - .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"), - .peri_base = 0x3f000000, - .ctrl_base = 0x40000000, - .clusterid = 0x0, - }, -#endif -}; - static void bcm2836_init(Object *obj) { BCM283XState *s = BCM283X(obj); BCM283XClass *bc = BCM283X_GET_CLASS(obj); - const BCM283XInfo *info = bc->info; int n; for (n = 0; n < BCM283X_NCPUS; n++) { object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, - info->cpu_type); + bc->cpu_type); } object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL); @@ -84,7 +58,6 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) { BCM283XState *s = BCM283X(dev); BCM283XClass *bc = BCM283X_GET_CLASS(dev); - const BCM283XInfo *info = bc->info; Object *obj; int n; @@ -102,14 +75,14 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) "sd-bus"); sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, - info->peri_base, 1); + bc->peri_base, 1); /* bcm2836 interrupt controller (and mailboxes, etc.) */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, info->ctrl_base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); @@ -118,11 +91,11 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) for (n = 0; n < BCM283X_NCPUS; n++) { /* TODO: this should be converted to a property of ARM_CPU */ - s->cpu[n].core.mp_affinity = (info->clusterid << 8) | n; + s->cpu[n].core.mp_affinity = (bc->clusterid << 8) | n; /* set periphbase/CBAR value for CPU-local registers */ if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", - info->peri_base, errp)) { + bc->peri_base, errp)) { return; } @@ -165,38 +138,59 @@ static Property bcm2836_props[] = { static void bcm283x_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); - BCM283XClass *bc = BCM283X_CLASS(oc); - bc->info = data; - dc->realize = bcm2836_realize; - device_class_set_props(dc, bcm2836_props); /* Reason: Must be wired up in code (see raspi_init() function) */ dc->user_creatable = false; } -static const TypeInfo bcm283x_type_info = { - .name = TYPE_BCM283X, - .parent = TYPE_DEVICE, - .instance_size = sizeof(BCM283XState), - .instance_init = bcm2836_init, - .class_size = sizeof(BCM283XClass), - .abstract = true, +static void bcm2836_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + BCM283XClass *bc = BCM283X_CLASS(oc); + + bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); + bc->peri_base = 0x3f000000; + bc->ctrl_base = 0x40000000; + bc->clusterid = 0xf; + dc->realize = bcm2836_realize; + device_class_set_props(dc, bcm2836_props); }; -static void bcm2836_register_types(void) +#ifdef TARGET_AARCH64 +static void bcm2837_class_init(ObjectClass *oc, void *data) { - int i; - - type_register_static(&bcm283x_type_info); - for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) { - TypeInfo ti = { - .name = bcm283x_socs[i].name, - .parent = TYPE_BCM283X, - .class_init = bcm283x_class_init, - .class_data = (void *) &bcm283x_socs[i], - }; - type_register(&ti); + DeviceClass *dc = DEVICE_CLASS(oc); + BCM283XClass *bc = BCM283X_CLASS(oc); + + bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); + bc->peri_base = 0x3f000000; + bc->ctrl_base = 0x40000000; + bc->clusterid = 0x0; + dc->realize = bcm2836_realize; + device_class_set_props(dc, bcm2836_props); +}; +#endif + +static const TypeInfo bcm283x_types[] = { + { + .name = TYPE_BCM2836, + .parent = TYPE_BCM283X, + .class_init = bcm2836_class_init, +#ifdef TARGET_AARCH64 + }, { + .name = TYPE_BCM2837, + .parent = TYPE_BCM283X, + .class_init = bcm2837_class_init, +#endif + }, { + .name = TYPE_BCM283X, + .parent = TYPE_DEVICE, + .instance_size = sizeof(BCM283XState), + .instance_init = bcm2836_init, + .class_size = sizeof(BCM283XClass), + .class_init = bcm283x_class_init, + .abstract = true, } -} +}; -type_init(bcm2836_register_types) +DEFINE_TYPES(bcm283x_types) -- cgit v1.2.3 From 25ea28845969c6f5b63b4b34c40c6cb743280b92 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 24 Oct 2020 19:01:21 +0200 Subject: hw/arm/bcm2836: Introduce BCM283XClass::core_count MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The BCM2835 has only one core. Introduce the core_count field to be able to use values different than BCM283X_NCPUS (4). Reviewed-by: Luc Michel Signed-off-by: Philippe Mathieu-Daudé Message-id: 20201024170127.3592182-4-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/bcm2836.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'hw/arm') diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 8f921d8e90..c5d46a8e80 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -23,6 +23,7 @@ typedef struct BCM283XClass { /*< public >*/ const char *name; const char *cpu_type; + unsigned core_count; hwaddr peri_base; /* Peripheral base address seen by the CPU */ hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ int clusterid; @@ -39,7 +40,7 @@ static void bcm2836_init(Object *obj) BCM283XClass *bc = BCM283X_GET_CLASS(obj); int n; - for (n = 0; n < BCM283X_NCPUS; n++) { + for (n = 0; n < bc->core_count; n++) { object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, bc->cpu_type); } @@ -149,6 +150,7 @@ static void bcm2836_class_init(ObjectClass *oc, void *data) BCM283XClass *bc = BCM283X_CLASS(oc); bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); + bc->core_count = BCM283X_NCPUS; bc->peri_base = 0x3f000000; bc->ctrl_base = 0x40000000; bc->clusterid = 0xf; @@ -163,6 +165,7 @@ static void bcm2837_class_init(ObjectClass *oc, void *data) BCM283XClass *bc = BCM283X_CLASS(oc); bc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); + bc->core_count = BCM283X_NCPUS; bc->peri_base = 0x3f000000; bc->ctrl_base = 0x40000000; bc->clusterid = 0x0; -- cgit v1.2.3 From 96c741d7ce94741234e4ccad0d08c0055dd48c7e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 24 Oct 2020 19:01:22 +0200 Subject: hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It makes no sense to set enabled-cpus=0 on single core SoCs. Reviewed-by: Luc Michel Signed-off-by: Philippe Mathieu-Daudé Message-id: 20201024170127.3592182-5-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/bcm2836.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'hw/arm') diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index c5d46a8e80..fcb2c9c3e7 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -34,6 +34,9 @@ typedef struct BCM283XClass { #define BCM283X_GET_CLASS(obj) \ OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) +static Property bcm2836_enabled_cores_property = + DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0); + static void bcm2836_init(Object *obj) { BCM283XState *s = BCM283X(obj); @@ -44,6 +47,10 @@ static void bcm2836_init(Object *obj) object_initialize_child(obj, "cpu[*]", &s->cpu[n].core, bc->cpu_type); } + if (bc->core_count > 1) { + qdev_property_add_static(DEVICE(obj), &bcm2836_enabled_cores_property); + qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); + } object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL); @@ -130,12 +137,6 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) } } -static Property bcm2836_props[] = { - DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, - BCM283X_NCPUS), - DEFINE_PROP_END_OF_LIST() -}; - static void bcm283x_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -155,7 +156,6 @@ static void bcm2836_class_init(ObjectClass *oc, void *data) bc->ctrl_base = 0x40000000; bc->clusterid = 0xf; dc->realize = bcm2836_realize; - device_class_set_props(dc, bcm2836_props); }; #ifdef TARGET_AARCH64 @@ -170,7 +170,6 @@ static void bcm2837_class_init(ObjectClass *oc, void *data) bc->ctrl_base = 0x40000000; bc->clusterid = 0x0; dc->realize = bcm2836_realize; - device_class_set_props(dc, bcm2836_props); }; #endif -- cgit v1.2.3 From f5600924ad42fba8eb5e30778baff6b4a5644070 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 24 Oct 2020 19:01:23 +0200 Subject: hw/arm/bcm2836: Split out common realize() code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The realize() function is clearly composed of two parts, each described by a comment: void realize() { /* common peripherals from bcm2835 */ ... /* bcm2836 interrupt controller (and mailboxes, etc.) */ ... } Split the two part, so we can reuse the common part with other SoCs from this family. Reviewed-by: Luc Michel Signed-off-by: Philippe Mathieu-Daudé Message-id: 20201024170127.3592182-6-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/bcm2836.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) (limited to 'hw/arm') diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index fcb2c9c3e7..7d975cf2f5 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -52,7 +52,10 @@ static void bcm2836_init(Object *obj) qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); } - object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL); + if (bc->ctrl_base) { + object_initialize_child(obj, "control", &s->control, + TYPE_BCM2836_CONTROL); + } object_initialize_child(obj, "peripherals", &s->peripherals, TYPE_BCM2835_PERIPHERALS); @@ -62,12 +65,11 @@ static void bcm2836_init(Object *obj) "vcram-size"); } -static void bcm2836_realize(DeviceState *dev, Error **errp) +static bool bcm283x_common_realize(DeviceState *dev, Error **errp) { BCM283XState *s = BCM283X(dev); BCM283XClass *bc = BCM283X_GET_CLASS(dev); Object *obj; - int n; /* common peripherals from bcm2835 */ @@ -76,7 +78,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) object_property_add_const_link(OBJECT(&s->peripherals), "ram", obj); if (!sysbus_realize(SYS_BUS_DEVICE(&s->peripherals), errp)) { - return; + return false; } object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals), @@ -84,6 +86,18 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, bc->peri_base, 1); + return true; +} + +static void bcm2836_realize(DeviceState *dev, Error **errp) +{ + BCM283XState *s = BCM283X(dev); + BCM283XClass *bc = BCM283X_GET_CLASS(dev); + int n; + + if (!bcm283x_common_realize(dev, errp)) { + return; + } /* bcm2836 interrupt controller (and mailboxes, etc.) */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) { -- cgit v1.2.3 From df6cf08dea890b691fafabd8a7ae8387ff2c8143 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 24 Oct 2020 19:01:24 +0200 Subject: hw/arm/bcm2836: Introduce the BCM2835 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Luc Michel Signed-off-by: Philippe Mathieu-Daudé Message-id: 20201024170127.3592182-7-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/bcm2836.c | 34 ++++++++++++++++++++++++++++++++++ hw/arm/raspi.c | 2 ++ 2 files changed, 36 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 7d975cf2f5..de7ade2878 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -89,6 +89,25 @@ static bool bcm283x_common_realize(DeviceState *dev, Error **errp) return true; } +static void bcm2835_realize(DeviceState *dev, Error **errp) +{ + BCM283XState *s = BCM283X(dev); + + if (!bcm283x_common_realize(dev, errp)) { + return; + } + + if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) { + return; + } + + /* Connect irq/fiq outputs from the interrupt controller. */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, + qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, + qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ)); +} + static void bcm2836_realize(DeviceState *dev, Error **errp) { BCM283XState *s = BCM283X(dev); @@ -159,6 +178,17 @@ static void bcm283x_class_init(ObjectClass *oc, void *data) dc->user_creatable = false; } +static void bcm2835_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + BCM283XClass *bc = BCM283X_CLASS(oc); + + bc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); + bc->core_count = 1; + bc->peri_base = 0x20000000; + dc->realize = bcm2835_realize; +}; + static void bcm2836_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -189,6 +219,10 @@ static void bcm2837_class_init(ObjectClass *oc, void *data) static const TypeInfo bcm283x_types[] = { { + .name = TYPE_BCM2835, + .parent = TYPE_BCM283X, + .class_init = bcm2835_class_init, + }, { .name = TYPE_BCM2836, .parent = TYPE_BCM283X, .class_init = bcm2836_class_init, diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index b5b30f0f38..30fafa59ec 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -70,6 +70,7 @@ FIELD(REV_CODE, MEMORY_SIZE, 20, 3); FIELD(REV_CODE, STYLE, 23, 1); typedef enum RaspiProcessorId { + PROCESSOR_ID_BCM2835 = 0, PROCESSOR_ID_BCM2836 = 1, PROCESSOR_ID_BCM2837 = 2, } RaspiProcessorId; @@ -78,6 +79,7 @@ static const struct { const char *type; int cores_count; } soc_property[] = { + [PROCESSOR_ID_BCM2835] = {TYPE_BCM2835, 1}, [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS}, [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS}, }; -- cgit v1.2.3 From ac6bc6ebb44d252b75398fbde887084dfd7bd31c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 24 Oct 2020 19:01:25 +0200 Subject: hw/arm/raspi: Add the Raspberry Pi A+ machine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Pi A is almost the first machine released. It uses a BCM2835 SoC which includes a ARMv6Z core. Example booting the machine using content from [*] (we use the device tree from the B model): $ qemu-system-arm -M raspi1ap -serial stdio \ -kernel raspberrypi/firmware/boot/kernel.img \ -dtb raspberrypi/firmware/boot/bcm2708-rpi-b-plus.dtb \ -append 'earlycon=pl011,0x20201000 console=ttyAMA0' [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST 2020 [ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d [ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache [ 0.000000] OF: fdt: Machine model: Raspberry Pi Model B+ ... [*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb Reviewed-by: Igor Mammedov Signed-off-by: Philippe Mathieu-Daudé Message-id: 20201024170127.3592182-8-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/raspi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 30fafa59ec..79fdd35460 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -319,6 +319,15 @@ static void raspi_machine_class_common_init(MachineClass *mc, mc->default_ram_id = "ram"; }; +static void raspi1ap_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); + + rmc->board_rev = 0x900021; /* Revision 1.1 */ + raspi_machine_class_common_init(mc, rmc->board_rev); +}; + static void raspi2b_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -343,6 +352,10 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data) static const TypeInfo raspi_machine_types[] = { { + .name = MACHINE_TYPE_NAME("raspi1ap"), + .parent = TYPE_RASPI_MACHINE, + .class_init = raspi1ap_machine_class_init, + }, { .name = MACHINE_TYPE_NAME("raspi2b"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi2b_machine_class_init, -- cgit v1.2.3 From 3c8f9927fd435bb8d4865c0f261ed206e14e139a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 24 Oct 2020 19:01:26 +0200 Subject: hw/arm/raspi: Add the Raspberry Pi Zero machine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Similarly to the Pi A, the Pi Zero uses a BCM2835 SoC (ARMv6Z core). The only difference between the revision 1.2 and 1.3 is the latter exposes a CSI camera connector. As we do not implement the Unicam peripheral, there is no point in exposing a camera connector :) Therefore we choose to model the 1.2 revision. Example booting the machine using content from [*]: $ qemu-system-arm -M raspi0 -serial stdio \ -kernel raspberrypi/firmware/boot/kernel.img \ -dtb raspberrypi/firmware/boot/bcm2708-rpi-zero.dtb \ -append 'printk.time=0 earlycon=pl011,0x20201000 console=ttyAMA0' [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.19.118+ (dom@buildbot) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1311 Mon Apr 27 14:16:15 BST 2020 [ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d [ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache [ 0.000000] OF: fdt: Machine model: Raspberry Pi Zero ... [*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/raspberrypi-kernel_1.20200512-2_armhf.deb Reviewed-by: Luc Michel Reviewed-by: Igor Mammedov Signed-off-by: Philippe Mathieu-Daudé Message-id: 20201024170127.3592182-9-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/raspi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 79fdd35460..0f5ea7e99b 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -319,6 +319,15 @@ static void raspi_machine_class_common_init(MachineClass *mc, mc->default_ram_id = "ram"; }; +static void raspi0_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); + + rmc->board_rev = 0x920092; /* Revision 1.2 */ + raspi_machine_class_common_init(mc, rmc->board_rev); +}; + static void raspi1ap_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -352,6 +361,10 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data) static const TypeInfo raspi_machine_types[] = { { + .name = MACHINE_TYPE_NAME("raspi0"), + .parent = TYPE_RASPI_MACHINE, + .class_init = raspi0_machine_class_init, + }, { .name = MACHINE_TYPE_NAME("raspi1ap"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi1ap_machine_class_init, -- cgit v1.2.3 From 5be94252d3497c29c0640e816903a148a4370153 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 24 Oct 2020 19:01:27 +0200 Subject: hw/arm/raspi: Add the Raspberry Pi 3 model A+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Pi 3A+ is a stripped down version of the 3B: - 512 MiB of RAM instead of 1 GiB - no on-board ethernet chipset Add it as it is a closer match to what we model. Reviewed-by: Igor Mammedov Signed-off-by: Philippe Mathieu-Daudé Message-id: 20201024170127.3592182-10-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/arm/raspi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 0f5ea7e99b..990509d385 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -348,6 +348,15 @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data) }; #ifdef TARGET_AARCH64 +static void raspi3ap_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); + + rmc->board_rev = 0x9020e0; /* Revision 1.0 */ + raspi_machine_class_common_init(mc, rmc->board_rev); +}; + static void raspi3b_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -373,6 +382,10 @@ static const TypeInfo raspi_machine_types[] = { .parent = TYPE_RASPI_MACHINE, .class_init = raspi2b_machine_class_init, #ifdef TARGET_AARCH64 + }, { + .name = MACHINE_TYPE_NAME("raspi3ap"), + .parent = TYPE_RASPI_MACHINE, + .class_init = raspi3ap_machine_class_init, }, { .name = MACHINE_TYPE_NAME("raspi3b"), .parent = TYPE_RASPI_MACHINE, -- cgit v1.2.3 From 43f828e155b443641765a1e933100a96f26be3dd Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Wed, 14 Oct 2020 20:33:55 +0100 Subject: arm/trace: Fix hex printing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use of 0x%d - make up our mind as 0x%x Signed-off-by: Dr. David Alan Gilbert Reviewed-by: Philippe Mathieu-Daudé Acked-by: Eric Auger Message-id: 20201014193355.53074-1-dgilbert@redhat.com Signed-off-by: Peter Maydell --- hw/arm/trace-events | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw/arm') diff --git a/hw/arm/trace-events b/hw/arm/trace-events index c8a4d80f6b..a335ee891d 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -41,7 +41,7 @@ smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64 smmuv3_decode_cd(uint32_t oas) "oas=%d" smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz, bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d" smmuv3_cmdq_cfgi_ste(int streamid) "streamid =%d" -smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d" +smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x" smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)" -- cgit v1.2.3 From 74de7145fd670bb8f86ceb2423c39c8dee37b820 Mon Sep 17 00:00:00 2001 From: Luc Michel Date: Sat, 10 Oct 2020 15:57:48 +0200 Subject: hw/arm/raspi: fix CPRMAN base address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CPRMAN (clock controller) was mapped at the watchdog/power manager address. It was also split into two unimplemented peripherals (CM and A2W) but this is really the same one, as shown by this extract of the Raspberry Pi 3 Linux device tree: watchdog@7e100000 { compatible = "brcm,bcm2835-pm\0brcm,bcm2835-pm-wdt"; [...] reg = <0x7e100000 0x114 0x7e00a000 0x24>; [...] }; [...] cprman@7e101000 { compatible = "brcm,bcm2835-cprman"; [...] reg = <0x7e101000 0x2000>; [...] }; Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Luc Michel Tested-by: Guenter Roeck Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/arm/bcm2835_peripherals.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hw/arm') diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 48909a43c3..10ed418e28 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -354,8 +354,8 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000); create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); - create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000); - create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000); + create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114); + create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x2000); create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20); -- cgit v1.2.3 From fc14176ba23de1386d8172d86a8006d9f8a555fc Mon Sep 17 00:00:00 2001 From: Luc Michel Date: Sat, 10 Oct 2020 15:57:49 +0200 Subject: hw/arm/raspi: add a skeleton implementation of the CPRMAN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The BCM2835 CPRMAN is the clock manager of the SoC. It is composed of a main oscillator, and several sub-components (PLLs, multiplexers, ...) to generate the BCM2835 clock tree. This commit adds a skeleton of the CPRMAN, with a dummy register read/write implementation. It embeds the main oscillator (xosc) from which all the clocks will be derived. Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Signed-off-by: Luc Michel Tested-by: Guenter Roeck Signed-off-by: Peter Maydell --- hw/arm/bcm2835_peripherals.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'hw/arm') diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 10ed418e28..d33ec54c41 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -121,6 +121,9 @@ static void bcm2835_peripherals_init(Object *obj) /* DWC2 */ object_initialize_child(obj, "dwc2", &s->dwc2, TYPE_DWC2_USB); + /* CPRMAN clock manager */ + object_initialize_child(obj, "cprman", &s->cprman, TYPE_BCM2835_CPRMAN); + object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr", OBJECT(&s->gpu_bus_mr)); } @@ -160,6 +163,13 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) return; } + /* CPRMAN clock manager */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->cprman), errp)) { + return; + } + memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0)); + memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0)); sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic)); @@ -355,7 +365,6 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000); create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114); - create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x2000); create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20); -- cgit v1.2.3 From 581bb849f749b6c51864989094399c77283b3d6c Mon Sep 17 00:00:00 2001 From: Luc Michel Date: Sat, 10 Oct 2020 15:57:59 +0200 Subject: hw/arm/bcm2835_peripherals: connect the UART clock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Connect the 'uart-out' clock from the CPRMAN to the PL011 instance. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Luc Michel Tested-by: Guenter Roeck Tested-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/arm/bcm2835_peripherals.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index d33ec54c41..dcff13433e 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -169,6 +169,8 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) } memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0)); + qdev_connect_clock_in(DEVICE(&s->uart0), "clk", + qdev_get_clock_out(DEVICE(&s->cprman), "uart-out")); memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0)); -- cgit v1.2.3 From 4204c5f70360dc1e527e65eb225d0688993fdcef Mon Sep 17 00:00:00 2001 From: Shashi Mallela Date: Mon, 26 Oct 2020 21:59:26 -0400 Subject: hw/watchdog: Implement SBSA watchdog device Generic watchdog device model implementation as per ARM SBSA v6.0 Signed-off-by: Shashi Mallela Message-id: 20201027015927.29495-2-shashi.mallela@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'hw/arm') diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7d040827af..0ef9e3c1d5 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -211,6 +211,7 @@ config SBSA_REF select PL031 # RTC select PL061 # GPIO select USB_EHCI_SYSBUS + select WDT_SBSA config SABRELITE bool -- cgit v1.2.3 From baabe7d03c0bd57735cff998d2369c1a4f7cfb5c Mon Sep 17 00:00:00 2001 From: Shashi Mallela Date: Mon, 26 Oct 2020 21:59:27 -0400 Subject: hw/arm/sbsa-ref: add SBSA watchdog device Included the newly implemented SBSA generic watchdog device model into SBSA platform Signed-off-by: Shashi Mallela Reviewed-by: Peter Maydell Message-id: 20201027015927.29495-3-shashi.mallela@linaro.org Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'hw/arm') diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 01863510d0..7d9e180c0d 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -40,6 +40,7 @@ #include "hw/qdev-properties.h" #include "hw/usb.h" #include "hw/char/pl011.h" +#include "hw/watchdog/sbsa_gwdt.h" #include "net/net.h" #include "qom/object.h" @@ -64,6 +65,9 @@ enum { SBSA_GIC_DIST, SBSA_GIC_REDIST, SBSA_SECURE_EC, + SBSA_GWDT, + SBSA_GWDT_REFRESH, + SBSA_GWDT_CONTROL, SBSA_SMMU, SBSA_UART, SBSA_RTC, @@ -104,6 +108,8 @@ static const MemMapEntry sbsa_ref_memmap[] = { [SBSA_GIC_DIST] = { 0x40060000, 0x00010000 }, [SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 }, [SBSA_SECURE_EC] = { 0x50000000, 0x00001000 }, + [SBSA_GWDT_REFRESH] = { 0x50010000, 0x00001000 }, + [SBSA_GWDT_CONTROL] = { 0x50011000, 0x00001000 }, [SBSA_UART] = { 0x60000000, 0x00001000 }, [SBSA_RTC] = { 0x60010000, 0x00001000 }, [SBSA_GPIO] = { 0x60020000, 0x00001000 }, @@ -134,6 +140,7 @@ static const int sbsa_ref_irqmap[] = { [SBSA_AHCI] = 10, [SBSA_EHCI] = 11, [SBSA_SMMU] = 12, /* ... to 15 */ + [SBSA_GWDT] = 16, }; static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) @@ -448,6 +455,20 @@ static void create_rtc(const SBSAMachineState *sms) sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); } +static void create_wdt(const SBSAMachineState *sms) +{ + hwaddr rbase = sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; + hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; + DeviceState *dev = qdev_new(TYPE_WDT_SBSA); + SysBusDevice *s = SYS_BUS_DEVICE(dev); + int irq = sbsa_ref_irqmap[SBSA_GWDT]; + + sysbus_realize_and_unref(s, &error_fatal); + sysbus_mmio_map(s, 0, rbase); + sysbus_mmio_map(s, 1, cbase); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); +} + static DeviceState *gpio_key_dev; static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) { @@ -731,6 +752,8 @@ static void sbsa_ref_init(MachineState *machine) create_rtc(sms); + create_wdt(sms); + create_gpio(sms); create_ahci(sms); -- cgit v1.2.3