From ec53b45bcd1f74f7a4c31331fa6d50b402cd6d26 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 20 Jan 2015 15:19:32 +0000 Subject: exec.c: Drop TARGET_HAS_ICE define and checks The TARGET_HAS_ICE #define is intended to indicate whether a target-* guest CPU implementation supports the breakpoint handling. However, all our guest CPUs have that support (the only two which do not define TARGET_HAS_ICE are unicore32 and openrisc, and in both those cases the bp support is present and the lack of the #define is just a bug). So remove the #define entirely: all new guest CPU support should include breakpoint handling as part of the basic implementation. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1420484960-32365-1-git-send-email-peter.maydell@linaro.org --- exec.c | 16 ---------------- linux-user/main.c | 4 ---- target-alpha/cpu.h | 2 -- target-arm/cpu.h | 2 -- target-cris/cpu.h | 2 -- target-i386/cpu.h | 2 -- target-lm32/cpu.h | 2 -- target-m68k/cpu.h | 2 -- target-microblaze/cpu.h | 2 -- target-mips/cpu.h | 1 - target-moxie/cpu.h | 2 -- target-ppc/cpu.h | 2 -- target-s390x/cpu.h | 2 -- target-sh4/cpu.h | 1 - target-sparc/cpu.h | 2 -- target-xtensa/cpu.h | 2 -- translate-all.c | 4 ++-- 17 files changed, 2 insertions(+), 48 deletions(-) diff --git a/exec.c b/exec.c index 081818e6e8..410371d7b8 100644 --- a/exec.c +++ b/exec.c @@ -553,7 +553,6 @@ void cpu_exec_init(CPUArchState *env) } } -#if defined(TARGET_HAS_ICE) #if defined(CONFIG_USER_ONLY) static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) { @@ -569,7 +568,6 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) } } #endif -#endif /* TARGET_HAS_ICE */ #if defined(CONFIG_USER_ONLY) void cpu_watchpoint_remove_all(CPUState *cpu, int mask) @@ -689,7 +687,6 @@ static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp, int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, CPUBreakpoint **breakpoint) { -#if defined(TARGET_HAS_ICE) CPUBreakpoint *bp; bp = g_malloc(sizeof(*bp)); @@ -710,15 +707,11 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, *breakpoint = bp; } return 0; -#else - return -ENOSYS; -#endif } /* Remove a specific breakpoint. */ int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) { -#if defined(TARGET_HAS_ICE) CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { @@ -728,27 +721,21 @@ int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) } } return -ENOENT; -#else - return -ENOSYS; -#endif } /* Remove a specific breakpoint by reference. */ void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint) { -#if defined(TARGET_HAS_ICE) QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); breakpoint_invalidate(cpu, breakpoint->pc); g_free(breakpoint); -#endif } /* Remove all matching breakpoints. */ void cpu_breakpoint_remove_all(CPUState *cpu, int mask) { -#if defined(TARGET_HAS_ICE) CPUBreakpoint *bp, *next; QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { @@ -756,14 +743,12 @@ void cpu_breakpoint_remove_all(CPUState *cpu, int mask) cpu_breakpoint_remove_by_ref(cpu, bp); } } -#endif } /* enable or disable single step mode. EXCP_DEBUG is returned by the CPU loop after each instruction */ void cpu_single_step(CPUState *cpu, int enabled) { -#if defined(TARGET_HAS_ICE) if (cpu->singlestep_enabled != enabled) { cpu->singlestep_enabled = enabled; if (kvm_enabled()) { @@ -775,7 +760,6 @@ void cpu_single_step(CPUState *cpu, int enabled) tb_flush(env); } } -#endif } void cpu_abort(CPUState *cpu, const char *fmt, ...) diff --git a/linux-user/main.c b/linux-user/main.c index 67b02316c1..ac39ff5493 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3436,10 +3436,8 @@ CPUArchState *cpu_copy(CPUArchState *env) CPUState *cpu = ENV_GET_CPU(env); CPUArchState *new_env = cpu_init(cpu_model); CPUState *new_cpu = ENV_GET_CPU(new_env); -#if defined(TARGET_HAS_ICE) CPUBreakpoint *bp; CPUWatchpoint *wp; -#endif /* Reset non arch specific state */ cpu_reset(new_cpu); @@ -3451,14 +3449,12 @@ CPUArchState *cpu_copy(CPUArchState *env) BP_CPU break/watchpoints are handled correctly on clone. */ QTAILQ_INIT(&cpu->breakpoints); QTAILQ_INIT(&cpu->watchpoints); -#if defined(TARGET_HAS_ICE) QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL); } QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL); } -#endif return new_env; } diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index d9b861f404..e276dbf9a2 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -32,8 +32,6 @@ #include "fpu/softfloat.h" -#define TARGET_HAS_ICE 1 - #define ELF_MACHINE EM_ALPHA #define ICACHE_LINE_SIZE 32 diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7ba55f0c2e..cd7a9e8e14 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -39,8 +39,6 @@ #include "fpu/softfloat.h" -#define TARGET_HAS_ICE 1 - #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ #define EXCP_PREFETCH_ABORT 3 diff --git a/target-cris/cpu.h b/target-cris/cpu.h index b88c147518..eea14b6462 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -29,8 +29,6 @@ #include "exec/cpu-defs.h" -#define TARGET_HAS_ICE 1 - #define ELF_MACHINE EM_CRIS #define EXCP_NMI 1 diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 3ecff96325..da3358787c 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -37,8 +37,6 @@ close to the modifying instruction */ #define TARGET_HAS_PRECISE_SMC -#define TARGET_HAS_ICE 1 - #ifdef TARGET_X86_64 #define ELF_MACHINE EM_X86_64 #define ELF_MACHINE_UNAME "x86_64" diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index 0dab6e89ab..e558c59499 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -30,8 +30,6 @@ struct CPULM32State; typedef struct CPULM32State CPULM32State; -#define TARGET_HAS_ICE 1 - #define ELF_MACHINE EM_LATTICEMICO32 #define NB_MMU_MODES 1 diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index f67bbcc646..3a1b9ab938 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -32,8 +32,6 @@ #define MAX_QREGS 32 -#define TARGET_HAS_ICE 1 - #define ELF_MACHINE EM_68K #define EXCP_ACCESS 2 /* Access (MMU) error. */ diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 6ccd06068c..5794f8991a 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -34,8 +34,6 @@ typedef struct CPUMBState CPUMBState; #include "mmu.h" #endif -#define TARGET_HAS_ICE 1 - #define ELF_MACHINE EM_MICROBLAZE #define EXCP_NMI 1 diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 8875c975e0..5ea61bceea 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -4,7 +4,6 @@ //#define DEBUG_OP #define ALIGNED_ONLY -#define TARGET_HAS_ICE 1 #define ELF_MACHINE EM_MIPS diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h index c5b12a5244..d809393670 100644 --- a/target-moxie/cpu.h +++ b/target-moxie/cpu.h @@ -26,8 +26,6 @@ #define CPUArchState struct CPUMoxieState -#define TARGET_HAS_ICE 1 - #define ELF_MACHINE 0xFEED /* EM_MOXIE */ #define MOXIE_EX_DIV0 0 diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index c62097bb8a..aae33a9237 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -79,8 +79,6 @@ #include "fpu/softfloat.h" -#define TARGET_HAS_ICE 1 - #if defined (TARGET_PPC64) #define ELF_MACHINE EM_PPC64 #else diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index 23ad336803..c123b6f023 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -886,8 +886,6 @@ int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code); uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst, uint64_t vr); -#define TARGET_HAS_ICE 1 - /* The value of the TOD clock for 1.1.1970. */ #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index a2e9e2c031..b2fb1990dd 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -23,7 +23,6 @@ #include "qemu-common.h" #define TARGET_LONG_BITS 32 -#define TARGET_HAS_ICE 1 #define ELF_MACHINE EM_SH diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 836f87f42f..0a50e5d113 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -31,8 +31,6 @@ #include "fpu/softfloat.h" -#define TARGET_HAS_ICE 1 - #if !defined(TARGET_SPARC64) #define ELF_MACHINE EM_SPARC #else diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index a1bfbf7acf..60ee563080 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -39,8 +39,6 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat.h" -#define TARGET_HAS_ICE 1 - #define NB_MMU_MODES 4 #define TARGET_PHYS_ADDR_SPACE_BITS 32 diff --git a/translate-all.c b/translate-all.c index 687ba7d177..4a1b64fd83 100644 --- a/translate-all.c +++ b/translate-all.c @@ -1451,7 +1451,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) return &tcg_ctx.tb_ctx.tbs[m_max]; } -#if defined(TARGET_HAS_ICE) && !defined(CONFIG_USER_ONLY) +#if !defined(CONFIG_USER_ONLY) void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) { ram_addr_t ram_addr; @@ -1467,7 +1467,7 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) + addr; tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); } -#endif /* TARGET_HAS_ICE && !defined(CONFIG_USER_ONLY) */ +#endif /* !defined(CONFIG_USER_ONLY) */ void tb_check_watchpoint(CPUState *cpu) { -- cgit v1.2.3