summaryrefslogtreecommitdiff
path: root/tcg/riscv
AgeCommit message (Expand)Author
2021-06-04tcg: Change parameters for tcg_target_const_matchRichard Henderson
2021-03-17tcg: Fix prototypes for tcg_out_vec_op and tcg_out_opMiroslav Rezanina
2021-02-02tcg: Remove TCG_TARGET_CON_SET_HRichard Henderson
2021-02-02tcg/riscv: Split out constraint sets to tcg-target-con-set.hRichard Henderson
2021-02-02tcg: Remove TCG_TARGET_CON_STR_HRichard Henderson
2021-02-02tcg/riscv: Split out target constraints to tcg-target-con-str.hRichard Henderson
2021-01-13tcg: Remove movi and dupi opcodesRichard Henderson
2021-01-07tcg: Constify TCGLabelQemuLdst.raddrRichard Henderson
2021-01-07tcg: Constify tcg_code_gen_epilogueRichard Henderson
2021-01-07tcg: Remove TCG_TARGET_SUPPORT_MIRRORRichard Henderson
2021-01-07tcg/riscv: Support split-wx code generationRichard Henderson
2021-01-07tcg/riscv: Remove branch-over-branch fallbackRichard Henderson
2021-01-07tcg/riscv: Fix branch range checksRichard Henderson
2021-01-07tcg: Add --accel tcg,split-wx propertyRichard Henderson
2021-01-07tcg: Adjust tb_target_set_jmp_target for split-wxRichard Henderson
2021-01-07tcg: Adjust tcg_register_jit for constRichard Henderson
2021-01-07tcg: Adjust tcg_out_call for constRichard Henderson
2021-01-07tcg: Move tcg epilogue pointer out of TCGContextRichard Henderson
2021-01-07tcg: Introduce INDEX_op_qemu_st8_i32Richard Henderson
2021-01-06Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell
2021-01-04tcg/riscv: Fix illegal shift instructionsZihao Yu
2021-01-02util: Extract flush_icache_range to cacheflush.cRichard Henderson
2020-10-08tcg: Remove TCG_CT_REGRichard Henderson
2020-10-08tcg: Drop union from TCGArgConstraintRichard Henderson
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini
2020-07-13tcg/riscv: Remove superfluous breaksLiao Pingfang
2020-01-15tcg: Search includes in the parent source directoryPhilippe Mathieu-Daudé
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen
2019-07-09tcg/riscv: Fix RISC-VH host build failureAlistair Francis
2019-06-10cpu: Move the softmmu tlb to CPUNegativeOffsetStateRichard Henderson
2019-06-10tcg: Create struct CPUTLBRichard Henderson
2019-05-13tcg: Return bool success from tcg_out_movRichard Henderson
2019-04-24tcg: Restart TB generation after out-of-line ldst overflowRichard Henderson
2019-04-24tcg: Add INDEX_op_extract2_{i32,i64}Richard Henderson
2019-01-28cputlb: Remove static tlb sizingRichard Henderson
2019-01-28tcg/riscv: enable dynamic TLB sizingRichard Henderson
2019-01-28tcg: introduce dynamic TLB sizingEmilio G. Cota
2018-12-26tcg/riscv: Add the target init codeAlistair Francis
2018-12-26tcg/riscv: Add the prologue generation and register the JITAlistair Francis
2018-12-26tcg/riscv: Add the out op decoderAlistair Francis
2018-12-26tcg/riscv: Add direct load and store instructionsAlistair Francis
2018-12-26tcg/riscv: Add slowpath load and store instructionsAlistair Francis
2018-12-26tcg/riscv: Add branch and jump instructionsAlistair Francis
2018-12-26tcg/riscv: Add the add2 and sub2 instructionsAlistair Francis
2018-12-26tcg/riscv: Add the out load and store instructionsAlistair Francis
2018-12-26tcg/riscv: Add the extract instructionsAlistair Francis
2018-12-26tcg/riscv: Add the mov and movi instructionAlistair Francis
2018-12-26tcg/riscv: Add the relocation functionsAlistair Francis
2018-12-26tcg/riscv: Add the instruction emittersAlistair Francis
2018-12-26tcg/riscv: Add the immediate encodersAlistair Francis
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 00:55:39 +0000