qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer.

Age	Commit message (Expand)	Author
2021-10-05	tcg: Rename TCGMemOpIdx to MemOpIdx	Richard Henderson
2021-10-05	tcg: Expand MO_SIZE to 3 bits	Richard Henderson
2021-09-21	tcg/riscv: Remove add with zero on user-only memory access	Richard Henderson
2021-07-09	tcg: Remove TCG_TARGET_HAS_goto_ptr	Richard Henderson
2021-06-29	tcg/riscv: Remove MO_BSWAP handling	Richard Henderson
2021-06-11	tcg: Move MAX_CODE_GEN_BUFFER_SIZE to tcg-target.h	Richard Henderson
2021-06-04	tcg: Change parameters for tcg_target_const_match	Richard Henderson
2021-03-17	tcg: Fix prototypes for tcg_out_vec_op and tcg_out_op	Miroslav Rezanina
2021-02-02	tcg: Remove TCG_TARGET_CON_SET_H	Richard Henderson
2021-02-02	tcg/riscv: Split out constraint sets to tcg-target-con-set.h	Richard Henderson
2021-02-02	tcg: Remove TCG_TARGET_CON_STR_H	Richard Henderson
2021-02-02	tcg/riscv: Split out target constraints to tcg-target-con-str.h	Richard Henderson
2021-01-13	tcg: Remove movi and dupi opcodes	Richard Henderson
2021-01-07	tcg: Constify TCGLabelQemuLdst.raddr	Richard Henderson
2021-01-07	tcg: Constify tcg_code_gen_epilogue	Richard Henderson
2021-01-07	tcg: Remove TCG_TARGET_SUPPORT_MIRROR	Richard Henderson
2021-01-07	tcg/riscv: Support split-wx code generation	Richard Henderson
2021-01-07	tcg/riscv: Remove branch-over-branch fallback	Richard Henderson
2021-01-07	tcg/riscv: Fix branch range checks	Richard Henderson
2021-01-07	tcg: Add --accel tcg,split-wx property	Richard Henderson
2021-01-07	tcg: Adjust tb_target_set_jmp_target for split-wx	Richard Henderson
2021-01-07	tcg: Adjust tcg_register_jit for const	Richard Henderson
2021-01-07	tcg: Adjust tcg_out_call for const	Richard Henderson
2021-01-07	tcg: Move tcg epilogue pointer out of TCGContext	Richard Henderson
2021-01-07	tcg: Introduce INDEX_op_qemu_st8_i32	Richard Henderson
2021-01-06	Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...	Peter Maydell
2021-01-04	tcg/riscv: Fix illegal shift instructions	Zihao Yu
2021-01-02	util: Extract flush_icache_range to cacheflush.c	Richard Henderson
2020-10-08	tcg: Remove TCG_CT_REG	Richard Henderson
2020-10-08	tcg: Drop union from TCGArgConstraint	Richard Henderson
2020-08-21	meson: rename included C source files to .c.inc	Paolo Bonzini
2020-07-13	tcg/riscv: Remove superfluous breaks	Liao Pingfang
2020-01-15	tcg: Search includes in the parent source directory	Philippe Mathieu-Daudé
2019-09-03	tcg: TCGMemOp is now accelerator independent MemOp	Tony Nguyen
2019-07-09	tcg/riscv: Fix RISC-VH host build failure	Alistair Francis
2019-06-10	cpu: Move the softmmu tlb to CPUNegativeOffsetState	Richard Henderson
2019-06-10	tcg: Create struct CPUTLB	Richard Henderson
2019-05-13	tcg: Return bool success from tcg_out_mov	Richard Henderson
2019-04-24	tcg: Restart TB generation after out-of-line ldst overflow	Richard Henderson
2019-04-24	tcg: Add INDEX_op_extract2_{i32,i64}	Richard Henderson
2019-01-28	cputlb: Remove static tlb sizing	Richard Henderson
2019-01-28	tcg/riscv: enable dynamic TLB sizing	Richard Henderson
2019-01-28	tcg: introduce dynamic TLB sizing	Emilio G. Cota
2018-12-26	tcg/riscv: Add the target init code	Alistair Francis
2018-12-26	tcg/riscv: Add the prologue generation and register the JIT	Alistair Francis
2018-12-26	tcg/riscv: Add the out op decoder	Alistair Francis
2018-12-26	tcg/riscv: Add direct load and store instructions	Alistair Francis
2018-12-26	tcg/riscv: Add slowpath load and store instructions	Alistair Francis
2018-12-26	tcg/riscv: Add branch and jump instructions	Alistair Francis
2018-12-26	tcg/riscv: Add the add2 and sub2 instructions	Alistair Francis