summaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)Author
2021-04-30target/arm: Add wrapper macros for accessing tbflagsRichard Henderson
2021-04-30target/arm: Rename TBFLAG_ANY, PSTATE_SSRichard Henderson
2021-04-30target/arm: Rename TBFLAG_A32, SCTLR_BRichard Henderson
2021-04-30target/arm: Fix decode of align in VLDST_singleRichard Henderson
2021-04-30target/arm: Remove log2_esize parameter to gen_mte_checkNRichard Henderson
2021-04-30target/arm: Simplify sve mte checkingRichard Henderson
2021-04-30target/arm: Rename mte_probe1 to mte_probeRichard Henderson
2021-04-30target/arm: Merge mte_check1, mte_checkNRichard Henderson
2021-04-30target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1Richard Henderson
2021-04-30target/arm: Fix unaligned checks for mte_check1, mte_probe1Richard Henderson
2021-04-30target/arm: Split out mte_probe_intRichard Henderson
2021-04-30target/arm: Fix mte_checkNRichard Henderson
2021-04-30target/arm: Make Thumb store insns UNDEF for Rn==1111Peter Maydell
2021-04-23target/s390x: fix s390_probe_access to check PAGE_WRITE_ORG for writeabilityAlex Bennée
2021-04-20target/mips/rel6_translate: Change license to GNU LGPL v2.1 (or later)Philippe Mathieu-Daudé
2021-04-17target/arm: drop CF_LAST_IO/dc->condjump checkAlex Bennée
2021-04-13target/mips: Fix TCG temporary leak in gen_cache_operation()Philippe Mathieu-Daudé
2021-04-12target/arm: Check PAGE_WRITE_ORG for MTE writeabilityRichard Henderson
2021-04-09i386: Add missing cpu feature bits in EPYC-Rome modelBabu Moger
2021-04-06Revert "target/arm: Make number of counters in PMCR follow the CPU"Peter Maydell
2021-04-05target/alpha: fix icount handling for timer instructionsPavel Dovgalyuk
2021-04-04Merge remote-tracking branch 'remotes/xtensa/tags/20210403-xtensa' into stagingPeter Maydell
2021-04-03target/xtensa: make xtensa_modules static on importMax Filippov
2021-04-03target/xtensa: fix meson.build rule for xtensa coresMax Filippov
2021-04-01hexagon: do not specify Python scripts as inputsPaolo Bonzini
2021-04-01hexagon: do not specify executables as inputsPaolo Bonzini
2021-04-01target/openrisc: fix icount handling for timer instructionsPavel Dovgalyuk
2021-04-01target/i386: Verify memory operand for lcall and ljmpRichard Henderson
2021-03-31target/ppc/kvm: Cache timebase frequencyGreg Kurz
2021-03-30target/arm: Make number of counters in PMCR follow the CPUPeter Maydell
2021-03-26s390x: move S390_ADAPTER_SUPPRESSIBLEGerd Hoffmann
2021-03-23Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210323'...Peter Maydell
2021-03-23target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fillRichard Henderson
2021-03-23target/arm: Make M-profile VTOR loads on reset handle memory aliasingPeter Maydell
2021-03-22target/riscv: Prevent lost illegal instruction exceptionsGeorg Kotheimer
2021-03-22target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer
2021-03-22target/riscv: Fix read and write accesses to vsip and vsieGeorg Kotheimer
2021-03-22target/riscv: Use background registers also for MSTATUS_MPVGeorg Kotheimer
2021-03-22target/riscv: Make VSTIP and VSEIP read-only in hipGeorg Kotheimer
2021-03-22target/riscv: Adjust privilege level for HLV(X)/HSV instructionsGeorg Kotheimer
2021-03-22target/riscv: flush TLB pages if PMP permission has been changedJim Shu
2021-03-22target/riscv: add log of PMP permission checkingJim Shu
2021-03-22target/riscv: propagate PMP permission to TLB pageJim Shu
2021-03-22target/riscv: fix vs() to return proper error codeFrank Chang
2021-03-22target/mips/mxu_translate.c: Fix array overrun for D16MIN/D16MAXPeter Maydell
2021-03-19i386: Make migration fail when Hyper-V reenlightenment was enabled but 'user_...Vitaly Kuznetsov
2021-03-19i386: Fix 'hypercall_hypercall' typoVitaly Kuznetsov
2021-03-19target/i386: svm: do not discard high 32 bits of EXITINFO1Paolo Bonzini
2021-03-19target/i386: fail if toggling LA57 in 64-bit modePaolo Bonzini
2021-03-19target/i386: allow modifying TCG phys-addr-bitsPaolo Bonzini