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2020-08-21meson: targetPaolo Bonzini
Similar to hw_arch, each architecture defines two sourceset which are placed in dictionaries target_arch and target_softmmu_arch. These are then picked up from there when building the per-emulator static_library. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21meson: convert target/s390x/gen-features.hMarc-André Lureau
Needed by linux-user/s390x/cpu_loop.c; this removes the only use of HOST_CC. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21meson: rename .inc.h files to .h.incPaolo Bonzini
Make it consistent with '.c.inc' and '.rst.inc'. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini
With Makefiles that have automatically generated dependencies, you generated includes are set as dependencies of the Makefile, so that they are built before everything else and they are available when first building the .c files. Alternatively you can use a fine-grained dependency, e.g. target/arm/translate.o: target/arm/decode-neon-shared.inc.c With Meson you have only one choice and it is a third option, namely "build at the beginning of the corresponding target"; the way you express it is to list the includes in the sources of that target. The problem is that Meson decides if something is a source vs. a generated include by looking at the extension: '.c', '.cc', '.m', '.C' are sources, while everything else is considered an include---including '.inc.c'. Use '.c.inc' to avoid this, as it is consistent with our other convention of using '.rst.inc' for included reStructuredText files. The editorconfig file is adjusted. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21trace: switch position of headers to what Meson requiresPaolo Bonzini
Meson doesn't enjoy the same flexibility we have with Make in choosing the include path. In particular the tracing headers are using $(build_root)/$(<D). In order to keep the include directives unchanged, the simplest solution is to generate headers with patterns like "trace/trace-audio.h" and place forwarding headers in the source tree such that for example "audio/trace.h" includes "trace/trace-audio.h". This patch is too ugly to be applied to the Makefiles now. It's only a way to separate the changes to the tracing header files from the Meson rewrite of the tracing logic. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-05target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64Peter Maydell
When a coprocessor instruction in an AArch32 guest traps to AArch32 Hyp mode, the syndrome register (HSR) includes Rt and Rt2 fields which are simply copies of the Rt and Rt2 fields from the trapped instruction. However, if the instruction is trapped from AArch32 to an AArch64 higher exception level, the Rt and Rt2 fields in the syndrome register (ESR_ELx) must be the AArch64 view of the register. This makes a difference if the AArch32 guest was in a mode other than User or System and it was using r13 or r14, or if it was in FIQ mode and using r8-r14. We don't know at translate time which AArch32 CPU mode we are in, so we leave the values we generate in our prototype syndrome register value at translate time as the raw Rt/Rt2 from the instruction, and instead correct them to the AArch64 view when we find we need to take an exception from AArch32 to AArch64 with one of these syndrome values. Fixes: https://bugs.launchpad.net/qemu/+bug/1879587 Reported-by: Julien Freche <julien@bedrocksystems.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200804193903.31240-1-peter.maydell@linaro.org
2020-08-05target/riscv/vector_helper: Fix build on 32-bit big endian hostsThomas Huth
The code currently fails to compile on 32-bit big endian hosts: target/riscv/vector_helper.c: In function 'vext_clear': target/riscv/vector_helper.c:154:16: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1); ^ target/riscv/vector_helper.c:155:16: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2); ^ cc1: all warnings being treated as errors We should not use "long long" (i.e. 64-bit) values here to avoid the problem. Switch to our QEMU_ALIGN_PTR_DOWN/UP macros instead. Fixes: 751538d5da ("add vector stride load and store instructions") Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200804170055.2851-3-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-08-04target/arm: Fix decode of LDRA[AB] instructionsPeter Collingbourne
These instructions use zero as the discriminator, not SP. Signed-off-by: Peter Collingbourne <pcc@google.com> Message-id: 20200804002849.30268-1-pcc@google.com Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-03target/arm: Avoid maybe-uninitialized warning with gcc 4.9Kaige Li
GCC version 4.9.4 isn't clever enough to figure out that all execution paths in disas_ldst() that use 'fn' will have initialized it first, and so it warns: /home/LiKaige/qemu/target/arm/translate-a64.c: In function ‘disas_ldst’: /home/LiKaige/qemu/target/arm/translate-a64.c:3392:5: error: ‘fn’ may be used uninitialized in this function [-Werror=maybe-uninitialized] fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), ^ /home/LiKaige/qemu/target/arm/translate-a64.c:3318:22: note: ‘fn’ was declared here AtomicThreeOpFn *fn; ^ Make it happy by initializing the variable to NULL. Signed-off-by: Kaige Li <likaige@loongson.cn> Message-id: 1596110248-7366-2-git-send-email-likaige@loongson.cn Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: Clean up commit message and note which gcc version this was] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-03target/arm: Fix AddPAC error indicationRichard Henderson
The definition of top_bit used in this function is one higher than that used in the Arm ARM psuedo-code, which put the error indication at top_bit - 1 at the wrong place, which meant that it wasn't visible to Auth. Fixing the definition of top_bit requires more changes, because its most common use is for the count of bits in top_bit:bot_bit, which would then need to be computed as top_bit - bot_bit + 1. For now, prefer the minimal fix to the error indication alone. Fixes: 63ff0ca94cb Reported-by: Derrick McKee <derrick.mckee@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200728195706.11087-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added comment about the divergence from the pseudocode] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-28Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20200727' into staging target-arm queue: * ACPI: Assert that we don't run out of the preallocated memory * hw/misc/aspeed_sdmc: Fix incorrect memory size * target/arm: Always pass cacheattr in S1_ptw_translate * docs/system/arm/virt: Document 'mte' machine option * hw/arm/boot: Fix PAUTH, MTE for EL3 direct kernel boot * target/arm: Improve IMPDEF algorithm for IRG # gpg: Signature made Mon 27 Jul 2020 16:18:38 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200727: target/arm: Improve IMPDEF algorithm for IRG hw/arm/boot: Fix MTE for EL3 direct kernel boot hw/arm/boot: Fix PAUTH for EL3 direct kernel boot docs/system/arm/virt: Document 'mte' machine option target/arm: Always pass cacheattr in S1_ptw_translate hw/misc/aspeed_sdmc: Fix incorrect memory size ACPI: Assert that we don't run out of the preallocated memory Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-27target/arm: Improve IMPDEF algorithm for IRGRichard Henderson
When GCR_EL1.RRND==1, the choosing of the random value is IMPDEF, and the kernel is not expected to have set RGSR_EL1. Force a non-zero value into SEED, so that we do not continually return the same tag. Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200724163853.504655-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-27target/arm: Always pass cacheattr in S1_ptw_translateRichard Henderson
When we changed the interface of get_phys_addr_lpae to require the cacheattr parameter, this spot was missed. The compiler is unable to detect the use of NULL vs the nonnull attribute here. Fixes: 7e98e21c098 Reported-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Jan Kiszka <jan.kiskza@siemens.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-27Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-fixes-for-rc2-270720-1' into staging Various fixes for rc2: - get shippable working again - semihosting bug fixes - tweak tb-size handling for low memory machines - i386 compound literal float fix - linux-user MAP_FIXED->MAP_NOREPLACE on fallback - docker binfmt_misc fixes - linux-user nanosleep fix - tests/vm drain console fixes # gpg: Signature made Mon 27 Jul 2020 09:45:31 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-fixes-for-rc2-270720-1: tests/vm: add shutdown timeout in basevm.py python/qemu: Change ConsoleSocket to optionally drain socket. python/qemu: Cleanup changes to ConsoleSocket linux-user, ppc: fix clock_nanosleep() for linux-user-ppc linux-user: fix clock_nanosleep() tests/docker: add support for DEB_KEYRING tests/docker: fix binfmt_misc image building tests/docker: fix update command due to python3 str/bytes distinction linux-user: don't use MAP_FIXED in pgd_find_hole_fallback target/i386: floatx80: avoid compound literals in static initializers accel/tcg: better handle memory constrained systems util/oslib-win32: add qemu_get_host_physmem implementation util: add qemu_get_host_physmem utility function semihosting: don't send the trailing '\0' semihosting: defer connect_chardevs a little more to use serialx shippable: add one more qemu to registry url Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-27target/i386: floatx80: avoid compound literals in static initializersLaszlo Ersek
Quoting ISO C99 6.7.8p4, "All the expressions in an initializer for an object that has static storage duration shall be constant expressions or string literals". The compound literal produced by the make_floatx80() macro is not such a constant expression, per 6.6p7-9. (An implementation may accept it, according to 6.6p10, but is not required to.) Therefore using "floatx80_zero" and make_floatx80() for initializing "f2xm1_table" and "fpatan_table" is not portable. And gcc-4.8 in RHEL-7.6 actually chokes on them: > target/i386/fpu_helper.c:871:5: error: initializer element is not constant > { make_floatx80(0xbfff, 0x8000000000000000ULL), > ^ We've had the make_floatx80_init() macro for this purpose since commit 3bf7e40ab914 ("softfloat: fix for C99", 2012-03-17), so let's use that macro again. Fixes: eca30647fc0 ("target/i386: reimplement f2xm1 using floatx80 operations") Fixes: ff57bb7b632 ("target/i386: reimplement fpatan using floatx80 operations") Signed-off-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Joseph Myers <joseph@codesourcery.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Link: https://lists.gnu.org/archive/html/qemu-devel/2017-08/msg06566.html Link: https://lists.gnu.org/archive/html/qemu-devel/2020-07/msg04714.html Message-Id: <20200716144251.23004-1-lersek@redhat.com> Message-Id: <20200724064509.331-8-alex.bennee@linaro.org>
2020-07-27pseries: fix kvmppc_set_fwnmi()Laurent Vivier
QEMU issues the ioctl(KVM_CAP_PPC_FWNMI) on the first vCPU. If the first vCPU is currently running, the vCPU mutex is held and the ioctl() cannot be done and waits until the mutex is released. This never happens and the VM is stuck. To avoid this deadlock, issue the ioctl on the same vCPU doing the RTAS call. The problem can be reproduced by booting a guest with several vCPUs (the probability to have the problem is (n - 1) / n, n = # of CPUs), and then by triggering a kernel crash with "echo c >/proc/sysrq-trigger". On the reboot, the kernel hangs after: ... [ 0.000000] ----------------------------------------------------- [ 0.000000] ppc64_pft_size = 0x0 [ 0.000000] phys_mem_size = 0x48000000 [ 0.000000] dcache_bsize = 0x80 [ 0.000000] icache_bsize = 0x80 [ 0.000000] cpu_features = 0x0001c06f8f4f91a7 [ 0.000000] possible = 0x0003fbffcf5fb1a7 [ 0.000000] always = 0x00000003800081a1 [ 0.000000] cpu_user_features = 0xdc0065c2 0xaee00000 [ 0.000000] mmu_features = 0x3c006041 [ 0.000000] firmware_features = 0x00000085455a445f [ 0.000000] physical_start = 0x8000000 [ 0.000000] ----------------------------------------------------- [ 0.000000] numa: NODE_DATA [mem 0x47f33c80-0x47f3ffff] Fixes: ec010c00665b ("ppc/spapr: KVM FWNMI should not be enabled until guest requests it") Cc: npiggin@gmail.com Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20200724083533.281700-1-lvivier@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-07-26Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200725' into stagingPeter Maydell
Fix some cputlb commentary Fix an hppa temporary leak Fix an i386 translation issue with loop insns # gpg: Signature made Sat 25 Jul 2020 17:03:59 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20200725: target/i386: Save cc_op before loop insns target/hppa: Free some temps in do_sub tcg: update comments for save_iotlb_data in cputlb Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-24target/i386: Save cc_op before loop insnsRichard Henderson
We forgot to update cc_op before these branch insns, which lead to losing track of the current eflags. Buglink: https://bugs.launchpad.net/qemu/+bug/1888165 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200720154028.477457-1-richard.henderson@linaro.org>
2020-07-24target/hppa: Free some temps in do_subRichard Henderson
Two temps allocated but not freed. Do enough subtractions within a single TB and one can run out of temps entirely. Fixes: b2167459ae ("target-hppa: Implement basic arithmetic") Buglink: https://bugs.launchpad.net/qemu/+bug/1880287 Tested-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200720174039.517902-1-richard.henderson@linaro.org>
2020-07-24Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2020-07-24' ↵Peter Maydell
into staging Error reporting patches patches for 2020-07-24 # gpg: Signature made Fri 24 Jul 2020 14:03:44 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-error-2020-07-24: qapi/error: Check format string argument in error_*prepend() sd/milkymist-memcard: Fix format string error: Strip trailing '\n' from error string arguments (again) coccinelle/err-bad-newline: Fix for Python 3, and add patterns Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-24error: Strip trailing '\n' from error string arguments (again)Markus Armbruster
Tracked down with scripts/coccinelle/err-bad-newline.cocci. Cc: Peter Xu <peterx@redhat.com> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20200722084048.1726105-3-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Xu <peterx@redhat.com>
2020-07-24Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/x86-next-for-5.1-pull-request' into staging x86 bug fix for -rc2 A fix from Vitaly Kuznetsov for a CPU reset bug reported by Jan Kiszka. # gpg: Signature made Thu 23 Jul 2020 20:10:40 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-for-5.1-pull-request: KVM: fix CPU reset wrt HF2_GIF_MASK Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-23KVM: fix CPU reset wrt HF2_GIF_MASKVitaly Kuznetsov
HF2_GIF_MASK is set in env->hflags2 unconditionally on CPU reset (see x86_cpu_reset()) but when calling KVM_SET_NESTED_STATE, KVM_STATE_NESTED_GIF_SET is only valid for nSVM as e.g. nVMX code looks like if (kvm_state->hdr.vmx.vmxon_pa == -1ull) { if (kvm_state->flags & ~KVM_STATE_NESTED_EVMCS) return -EINVAL; } Also, when adjusting the environment after KVM_GET_NESTED_STATE we need not reset HF2_GIF_MASK on VMX as e.g. x86_cpu_pending_interrupt() expects it to be set. Alternatively, we could've made env->hflags2 SVM-only. Reported-by: Jan Kiszka <jan.kiszka@siemens.com> Fixes: b16c0e20c742 ("KVM: add support for AMD nested live migration") Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20200723142701.2521161-1-vkuznets@redhat.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-07-22target/riscv: Fix the range of pmpcfg of CSR funcion tableZong Li
The range of Physical Memory Protection should be from CSR_PMPCFG0 to CSR_PMPCFG3, not to CSR_PMPADDR9. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Message-Id: <eae49e9252c9596e4f3bdb471772f79235141a87.1595335112.git.zong.li@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-22target/riscv: fix vector index load/store constraintsLIU Zhiwei
Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-22target/riscv: Quiet Coverity complains about vamo*LIU Zhiwei
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200721133742.2298-1-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-20hw/arm/virt: Enable MTE via a machine propertyRichard Henderson
Control this cpu feature via a machine property, much as we do with secure=on, since both require specialized support in the machine setup to be functional. Default MTE to off, since this feature implies extra overhead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200713213341.590275-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-16i386: hvf: Explicitly set CR4 guest/host maskRoman Bolshakov
Removal of register reset omitted initialization of CR4 guest/host mask. x86_64 guests aren't booting without it. Fixes: 5009ef22c6bb2 ("i386: hvf: Don't duplicate register reset") Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200714090726.41082-1-r.bolshakov@yadro.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-07-16target/i386: add the missing vmx features for Skylake-Server and ↵Chenyi Qiang
Cascadelake-Server CPU models Add the missing vmx features in Skylake-Server and Cascadelake-Server CPU models based on the output of Paolo's script. Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Message-Id: <20200714084148.26690-4-chenyi.qiang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-07-16target/i386: fix model number and add missing features for Icelake-Server ↵Chenyi Qiang
CPU model Add the missing features(sha_ni, avx512ifma, rdpid, fsrm, vmx-rdseed-exit, vmx-pml, vmx-eptp-switching) and change the model number to 106 in the Icelake-Server-v4 CPU model. Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Message-Id: <20200714084148.26690-3-chenyi.qiang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-07-16target/i386: add fast short REP MOV supportChenyi Qiang
For CPUs support fast short REP MOV[CPUID.(EAX=7,ECX=0):EDX(bit4)], e.g Icelake and Tigerlake, expose it to the guest VM. Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com> Message-Id: <20200714084148.26690-2-chenyi.qiang@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-07-16i386/cpu: Don't add unavailable_features to env->user_featuresXiaoyao Li
Features unavailable due to absent of their dependent features should not be added to env->user_features. env->user_features only contains the feature explicity specified with -feature/+feature by user. Fixes: 99e24dbdaa68 ("target/i386: introduce generic feature dependency mechanism") Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20200713174436.41070-3-xiaoyao.li@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-07-16i368/cpu: Clear env->user_features after loading versioned CPU modelXiaoyao Li
Features defined in versioned CPU model are recorded in env->user_features since they are updated as property. It's unwated because they are not user specified. Simply clear env->user_features as a fix. It won't clear user specified features because user specified features are filled to env->user_features later in x86_cpu_expand_features(). Cc: Chenyi Qiang <chenyi.qiang@intel.com> Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20200713174436.41070-2-xiaoyao.li@intel.com> [ehabkost: fix coding style] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-07-15Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-next-20200714' ↵Peter Maydell
into staging MIPS patches for 5.1 - A pair of fixes, - Add Huacai Chen as MIPS KVM maintainer, - Add Jiaxun Yang as designated MIPS TCG reviewer. CI jobs results: . https://travis-ci.org/github/philmd/qemu/builds/708079271 . https://gitlab.com/philmd/qemu/-/pipelines/166528104 . https://cirrus-ci.com/build/6483996878045184 # gpg: Signature made Tue 14 Jul 2020 20:59:58 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/mips-next-20200714: MAINTAINERS: Adjust MIPS maintainership (add Huacai Chen & Jiaxun Yang) target/mips: Fix ADD.S FPU instruction target/mips: Remove identical if/else branches Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-14target/mips: Fix ADD.S FPU instructionAlex Richardson
After merging latest QEMU upstream into our CHERI fork, I noticed that some of the FPU tests in our MIPS baremetal testsuite [*] started failing. It turns out commit 1ace099f2a accidentally changed add.s into a subtract. [*] https://github.com/CTSRD-CHERI/cheritest Fixes: 1ace099f2a ("target/mips: fpu: Demacro ADD.<D|S|PS>") Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200703161515.25966-1-Alexander.Richardson@cl.cam.ac.uk> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-07-14target/mips: Remove identical if/else branchesAleksandar Markovic
Remove the segment: if (other_tc == other->current_tc) { tccause = other->CP0_Cause; } else { tccause = other->CP0_Cause; } Original contributor can't remember what was his intention. Fixes: 5a25ce9487 ("mips: Hook in more reg accesses via mttr/mftr") Buglink: https://bugs.launchpad.net/qemu/+bug/1885718 Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20200701182559.28841-2-aleksandar.qemu.devel@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-07-14Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20200713' into staging This is a colection of bug fixes and small imrprovements for RISC-V. This includes some vector extensions fixes, a PMP bug fix, OpenTitan UART bug fix and support for OpenSBI dynamic firmware. # gpg: Signature made Tue 14 Jul 2020 01:29:44 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200713: target/riscv: Fix pmp NA4 implementation tcg/riscv: Remove superfluous breaks hw/char: Convert the Ibex UART to use the registerfields API hw/char: Convert the Ibex UART to use the qdev Clock model target/riscv: fix vill bit index in vtype register target/riscv: fix return value of do_opivx_widen() target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion hw/riscv: Modify MROM size to end at 0x10000 RISC-V: Support 64 bit start address riscv: Add opensbi firmware dynamic support RISC-V: Copy the fdt in dram instead of ROM riscv: Unify Qemu's reset vector code path hw/riscv: virt: Sort the SoC memmap table entries MAINTAINERS: Add an entry for OpenSBI firmware Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-14Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-07-13' into ↵Peter Maydell
staging NBD patches for 2020-07-13 - fix off-by-one truncation in corner-case name display - use fcntl correctly - iotest cleanups that enable testing an upcoming fix for NBD close # gpg: Signature made Mon 13 Jul 2020 15:11:35 BST # gpg: using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" [full] # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" [full] # gpg: aka "[jpeg image of size 6874]" [full] # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2020-07-13: iotests.py: filter_testfiles(): filter SOCK_DIR too iotests.py: QemuIoInteractive: print output on failure iotests: QemuIoInteractive: use qemu_io_args_no_fmt hax: Fix setting of FD_CLOEXEC nbd: Avoid off-by-one in long export name truncation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-13target/riscv: Fix pmp NA4 implementationAlexandre Mergnat
The end address calculation for NA4 mode is wrong because the address used isn't shifted. It doesn't watch 4 bytes but a huge range because the end address calculation is wrong. The solution is to use the shifted address calculated for start address variable. Modifications are tested on Zephyr OS userspace test suite which works for other RISC-V boards (E31 and E34 core). Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200706084550.24117-1-amergnat@baylibre.com Message-Id: <20200706084550.24117-1-amergnat@baylibre.com> [ Changes by AF: - Improve the commit title and message ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-13target/riscv: fix vill bit index in vtype registerFrank Chang
vill bit is at vtype[XLEN-1]. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200710104920.13550-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-13target/riscv: fix return value of do_opivx_widen()Frank Chang
do_opivx_widen() should return false if check function returns false. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200710104920.13550-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-13target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()Frank Chang
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200710104920.13550-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-13target/riscv: fix rsub gvec tcg_assert_listed_vecop assertionFrank Chang
gvec should provide vecop_list to avoid: "tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200710104920.13550-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-13hax: Fix setting of FD_CLOEXECEric Blake
Blindly setting FD_CLOEXEC without a read-modify-write will inadvertently clear any other intentionally-set bits, such as a proposed new bit for designating a fd that must behave in 32-bit mode. Use our wrapper function instead of an incorrect hand-rolled version. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20200420175309.75894-2-eblake@redhat.com> Reviewed-by: Colin Xu <colin.xu@intel.com>
2020-07-13target/nios2: Use gen_io_start around wrctl instructionWentong Wu
wrctl instruction on nios2 target will cause checking cpu interrupt but tcg_handle_interrupt() will call cpu_abort() if the CPU gets an interrupt while it's not in 'can do IO' state, so add gen_io_start around wrctl instruction. Also at the same time, end the onging TB with DISAS_UPDATE. Signed-off-by: Wentong Wu <wentong.wu@intel.com> Message-id: 20200710233433.19729-3-wentong.wu@intel.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-13target/nios2: in line the semantics of DISAS_UPDATE with other targetsWentong Wu
In line the semantics of DISAS_UPDATE on nios2 target with other targets which is to explicitly write the PC back into the cpu state before doing a tcg_gen_exit_tb(). Signed-off-by: Wentong Wu <wentong.wu@intel.com> Message-id: 20200710233433.19729-2-wentong.wu@intel.com Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-13target/nios2: add DISAS_NORETURN case for nothing more to generateWentong Wu
Add DISAS_NORETURN case for nothing more to generate because at runtime execution will never return from some helper call. And at the same time replace DISAS_UPDATE in t_gen_helper_raise_exception and gen_exception with the newly added DISAS_NORETURN. Signed-off-by: Wentong Wu <wentong.wu@intel.com> Message-id: 20200710233433.19729-1-wentong.wu@intel.com Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-13target/arm: Don't do raw writes for PMINTENCLRAaron Lindsay
Raw writes to this register when in KVM mode can cause interrupts to be raised (even when the PMU is disabled). Because the underlying state is already aliased to PMINTENSET (which already provides raw write functions), we can safely disable raw accesses to PMINTENCLR entirely. Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Message-id: 20200707152616.1917154-1-aaron@os.amperecomputing.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-13target/arm: Fix mtedesc for do_mem_zpzRichard Henderson
The mtedesc that was constructed was not actually passed in. Found by Coverity (CID 1429996). Fixes: d28d12f008e Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200706202345.193676-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-07-11Merge remote-tracking branch 'remotes/philmd-gitlab/tags/avr-port-20200711' ↵Peter Maydell
into staging 8bit AVR port from Michael Rolnik. Michael started to work on the AVR port few years ago [*] and kept improving the code over various series. List of people who help him (in chronological order): - Richard Henderson - Sarah Harris and Edward Robbins - Philippe Mathieu-Daudé and Aleksandar Markovic - Pavel Dovgalyuk - Thomas Huth [*] The oldest contribution I could find on the list is from 2016: https://lists.nongnu.org/archive/html/qemu-devel/2016-06/msg02985.html Tests included: $ avocado --show=app run -t arch:avr tests/acceptance/ Fetching asset from tests/acceptance/machine_avr6.py:AVR6Machine.test_freertos (1/1) tests/acceptance/machine_avr6.py:AVR6Machine.test_freertos: PASS (2.13 s) RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 JOB TIME : 2.35 s $ make check-qtest-avr TEST check-qtest-avr: tests/qtest/boot-serial-test TEST check-qtest-avr: tests/qtest/cdrom-test TEST check-qtest-avr: tests/qtest/device-introspect-test TEST check-qtest-avr: tests/qtest/machine-none-test TEST check-qtest-avr: tests/qtest/qmp-test TEST check-qtest-avr: tests/qtest/qmp-cmd-test TEST check-qtest-avr: tests/qtest/qom-test TEST check-qtest-avr: tests/qtest/test-hmp TEST check-qtest-avr: tests/qtest/qos-test CI results: . https://cirrus-ci.com/build/5697049146425344 . https://gitlab.com/philmd/qemu/-/pipelines/165328058 . https://travis-ci.org/github/philmd/qemu/builds/705817933 . https://app.shippable.com/github/philmd/qemu/runs/822/summary/console # gpg: Signature made Sat 11 Jul 2020 10:03:11 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/avr-port-20200711: (32 commits) target/avr/disas: Fix store instructions display order target/avr/cpu: Fix $PC displayed address target/avr/cpu: Drop tlb_flush() in avr_cpu_reset() target/avr: Add section into QEMU documentation tests/acceptance: Test the Arduino MEGA2560 board tests/boot-serial: Test some Arduino boards (AVR based) hw/avr: Add limited support for some Arduino boards hw/avr: Add some ATmega microcontrollers hw/avr: Add support for loading ELF/raw binaries hw/misc: avr: Add limited support for power reduction device hw/timer: avr: Add limited support for 16-bit timer peripheral hw/char: avr: Add limited support for USART peripheral tests/machine-none: Add AVR support target/avr: Register AVR support with the rest of QEMU target/avr: Add support for disassembling via option '-d in_asm' target/avr: Initialize TCG register variables target/avr: Add instruction translation - CPU main translation function target/avr: Add instruction translation - MCU Control Instructions target/avr: Add instruction translation - Bit and Bit-test Instructions target/avr: Add instruction translation - Data Transfer Instructions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 03:52:21 +0000