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AgeCommit message (Expand)Author
2019-06-17target/arm: Only implement doubles if the FPU supports themPeter Maydell
2019-06-17target/arm: Fix typos in trans function prototypesPeter Maydell
2019-06-17target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1dPeter Maydell
2019-06-17target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16Peter Maydell
2019-06-17target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32Peter Maydell
2019-06-17target/arm: Stop using cpu_F0s in Neon VCVT fixed-point opsPeter Maydell
2019-06-17target/arm: Stop using cpu_F0s for Neon f32/s32 VCVTPeter Maydell
2019-06-17target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_FPeter Maydell
2019-06-17target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US]Peter Maydell
2019-06-17target/arm: Stop using cpu_F0s for NEON_2RM_VRINT*Peter Maydell
2019-06-17target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_FPeter Maydell
2019-06-17target/arm: Stop using cpu_F0s for NEON_2RM_VABS_FPeter Maydell
2019-06-17target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_immPeter Maydell
2019-06-17target/arm: Move vfp_expand_imm() to translate.[ch]Peter Maydell
2019-06-17target/arm: Allow M-profile CPUs to disable the DSP extension via CPU propertyPeter Maydell
2019-06-17target/arm: Allow VFP and Neon to be disabled via a CPU propertyPeter Maydell
2019-06-13target/arm: Fix short-vector increment behaviourPeter Maydell
2019-06-13target/arm: Convert float-to-integer VCVT insns to decodetreePeter Maydell
2019-06-13target/arm: Convert VCVT fp/fixed-point conversion insns to decodetreePeter Maydell
2019-06-13target/arm: Convert VJCVT to decodetreePeter Maydell
2019-06-13target/arm: Convert integer-to-float insns to decodetreePeter Maydell
2019-06-13target/arm: Convert double-single precision conversion insns to decodetreePeter Maydell
2019-06-13target/arm: Convert VFP round insns to decodetreePeter Maydell
2019-06-13target/arm: Convert the VCVT-to-f16 insns to decodetreePeter Maydell
2019-06-13target/arm: Convert the VCVT-from-f16 insns to decodetreePeter Maydell
2019-06-13target/arm: Convert VFP comparison insns to decodetreePeter Maydell
2019-06-13target/arm: Convert VMOV (register) to decodetreePeter Maydell
2019-06-13target/arm: Convert VSQRT to decodetreePeter Maydell
2019-06-13target/arm: Convert VNEG to decodetreePeter Maydell
2019-06-13target/arm: Convert VABS to decodetreePeter Maydell
2019-06-13target/arm: Convert VMOV (imm) to decodetreePeter Maydell
2019-06-13target/arm: Convert VFP fused multiply-add insns to decodetreePeter Maydell
2019-06-13target/arm: Convert VDIV to decodetreePeter Maydell
2019-06-13target/arm: Convert VSUB to decodetreePeter Maydell
2019-06-13target/arm: Convert VADD to decodetreePeter Maydell
2019-06-13target/arm: Convert VNMUL to decodetreePeter Maydell
2019-06-13target/arm: Convert VMUL to decodetreePeter Maydell
2019-06-13target/arm: Convert VFP VNMLA to decodetreePeter Maydell
2019-06-13target/arm: Convert VFP VNMLS to decodetreePeter Maydell
2019-06-13target/arm: Convert VFP VMLS to decodetreePeter Maydell
2019-06-13target/arm: Convert VFP VMLA to decodetreePeter Maydell
2019-06-13target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0dPeter Maydell
2019-06-13target/arm: Convert the VFP load/store multiple insns to decodetreePeter Maydell
2019-06-13target/arm: Convert VFP VLDR and VSTR to decodetreePeter Maydell
2019-06-13target/arm: Convert VFP two-register transfer insns to decodetreePeter Maydell
2019-06-13target/arm: Convert "single-precision" register moves to decodetreePeter Maydell
2019-06-13target/arm: Convert "double-precision" register moves to decodetreePeter Maydell
2019-06-13target/arm: Add helpers for VFP register loads and storesPeter Maydell
2019-06-13target/arm: Move the VFP trans_* functions to translate-vfp.inc.cPeter Maydell
2019-06-13target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetreePeter Maydell
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